FORMAL VERIFICATION COMPARISON POINT MATCHING METHOD AND SYSTEM, PROCESSOR, AND MEMORY

WIPO Patent Application WO/2022/000576

A1

Disclosed are a formal verification comparison point matching method and system, a processor, and a memory. The method comprises: receiving a reference circuit model and an implemented circuit model of a sequential circuit to be verified; controlling test vectors of comparison points to be matched of the reference circuit model and the implemented circuit model to be randomly generated, so that binary tree matching can be performed on output values of the comparison points of the reference circuit model and the implemented circuit model; matching, on the basis of binary tree matching, the output values of the comparison points to be matched of the reference circuit model with the output values of the comparison points to be matched of the implemented circuit model until all the comparison points of the reference circuit model and the implemented circuit model are successfully matched on a one-to-one basis, and indicating that the verification is successful; and if the comparison points to be matched of the reference circuit model and the implemented circuit model fail to be matched, indicating that the verification fails. By means of the present invention, the matching complexity of corresponding comparison points in the equivalence checking process of a sequential circuit is reduced, the matching time is reduced, and the memory consumption is reduced.

ZHANG YAN (CN)
LIU MEIHUA (CN)
HUANG GUOYONG (CN)
JIN YUFENG (CN)

PCT/CN2020/102281

January 06, 2022

July 16, 2020

Click for automatic bibliography generation  

SMIT GROUP LTD (CN)

G06F30/398; G06F30/3312; G06F30/3323

US6408424B1	2002-06-18
CN1560769A	2005-01-05
CN107798203A	2018-03-13

SHENZHEN KANGHONG INTELLECTUAL PROPERTY AGENT CO., LTD. (CN)

View/Download PDF      PDF Help

Previous Patent: INFRARED EMISSION MODULE FOR WIDE-ANGLE TIME OF FLY OPTICAL RANGING AND MODULE THEREOF

Next Patent: LOUDSPEAKER