Title:
FORMING METHOD FOR RESISTANCE-CHANGE NON-VOLATILE MEMORY ELEMENT, AND RESISTANCE-CHANGE NON-VOLATILE MEMORY DEVICE
Document Type and Number:
WIPO Patent Application WO/2010/143396
Kind Code:
A1
Abstract:
Disclosed is an optimal forming method for a resistance-change element, wherein the operating window of the resistance-change element can be maximized. This forming method initializes the resistance-change element (100) and includes an assessing step (S35) of assessing whether the resistance value of the resistance-change element (100) is less than when in a high resistance state, and an applying step (S36) of applying, when it has been assessed that the resistance value is not low ("no" at S35), a voltage pulse which does not exceed a voltage obtained by adding a forming margin to a forming voltage. The assessing step (S35) and applying step (S36) are repeated for all memory cells in a memory array (202) (S34 to S37).
Inventors:
KAWAI KEN
SHIMAKAWA KAZUHIKO
MURAOKA SHUNSAKU
AZUMA RYOTARO
SHIMAKAWA KAZUHIKO
MURAOKA SHUNSAKU
AZUMA RYOTARO
Application Number:
PCT/JP2010/003765
Publication Date:
December 16, 2010
Filing Date:
June 04, 2010
Export Citation:
Assignee:
PANASONIC CORP (JP)
KAWAI KEN
SHIMAKAWA KAZUHIKO
MURAOKA SHUNSAKU
AZUMA RYOTARO
KAWAI KEN
SHIMAKAWA KAZUHIKO
MURAOKA SHUNSAKU
AZUMA RYOTARO
International Classes:
G11C13/00
Domestic Patent References:
| WO2008149484A1 | 2008-12-11 |
Foreign References:
| JP2008210441A | 2008-09-11 |
Attorney, Agent or Firm:
NII, Hiromori (JP)
New house extensive 守 (JP)
New house extensive 守 (JP)
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