Title:
FPGA CIRCUIT AND METHOD FOR PROCESSING CONFIGURATION FILE THEREOF
Document Type and Number:
WIPO Patent Application WO/2017/113333
Kind Code:
A1
Abstract:
An FPGA circuit, comprising: a configuration memory for storing an FPGA configuration file, wherein the configuration file comprises configuration data, an ECC code and a CRC code; a hardware ECC decoder for performing error correction and error detection on the configuration data by using the ECC code; a hardware CRC decoder for performing error correction on the configuration data by using the CRC code; and a single event upset controller for reading back the configuration file, performing detection and error correction on the readback configuration file by using the hardware ECC decoder and the hardware CRC decoder, recording an error state and information about the configuration file, generating corresponding control according to the detection states of the hardware ECC and CRC decoders, sending an error signal to a system-level application, and requesting to reconfigure the FPGA configuration file. By using the circuit, the capability of an FPGA for supporting single event upset can be enhanced, so that the FPGA can be applied to space navigation and aviation or other fields relatively sensitive to an error of a device.
Inventors:
HE KE (CN)
Application Number:
PCT/CN2015/100196
Publication Date:
July 06, 2017
Filing Date:
December 31, 2015
Export Citation:
Assignee:
CAPITAL MICROELECTRONICS CO LTD (CN)
International Classes:
G11C29/00
Foreign References:
| US8516339B1 | 2013-08-20 | |||
| US7408381B1 | 2008-08-05 | |||
| US7576557B1 | 2009-08-18 | |||
| CN102203740A | 2011-09-28 | |||
| CN102566982A | 2012-07-11 |
Attorney, Agent or Firm:
E-TONE INTELLECTUAL PROPERTY FIRM (CN)
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