RELATED APPLICATIONS

[001] The application claims the benefit of U.S. Non-Provisional Patent Application No. 16/269,931 filed on February 7, 2019, and entitled“Fractional Valley Switching Controller”, which claims the benefit of U.S. Provisional Patent

Application No. 62/630,639 filed on February 14, 2018, and entitled“Fractional Valley Switching Controller,” and is related to U.S. Patent Application No.

16/020,496 filed on June 27, 2018, and entitled“Switch-Mode Power Supply

Controller”; all of which are hereby incorporated by reference in their entirety for all purposes.

BACKGROUND

[002] Switch-mode power supplies (SMPSs) (“power converters”) are widely utilized in consumer, industrial and medical applications to provide well- regulated power while maintaining high power processing efficiency, tight-output voltage regulation, and reduced conducted and radiated electromagnetic interference (EMI).

[003] To meet these conflicting goals, state-of-the-art power converters (fly back converters, forward converters, boost converters, buck converters, and so on) commonly utilize quasi-resonant control methods. Quasi-resonant control methods induce a resonant waveform having sinusoidal voltage oscillations at the drains of one or more semiconductor switches of the power converter. Through well-timed control actions, the semiconductor switches are turned on at the instants where the drain voltage is minimum (i.e., valley switching), thus minimizing the semiconductor switching losses and drain-source dv/dt slope, leading to increased power processing efficiency and reduced electromagnetic interference (EMI).

[004] To maintain these benefits across an entire operating range of the power converter, it is often necessary to“hop” between the valleys of the resonant waveform in such a way as to minimize the sum of the conduction and switching losses (which are generally inversely proportional to each other). However, during the valley hop transitions, output voltage disturbances are introduced. Furthermore, if there are frequent and/or repeated low-frequency mode transitions, audible noise may be generated by the magnetic and/or capacitive elements of the power converter.

[005] Typically, this issue is partially addressed by introducing large valley hopping hysteresis constraints. However, such methods negatively affect power processing efficiency and eliminate any potential spread- spectrum benefits from more frequent valley hopping. In addition, a large output voltage disturbance is still introduced as a result of such valley mode transitions.

SUMMARY

[006] Some embodiments described herein provide a power converter controller that includes a fractional valley controller configured to determine a target number of valleys of a resonant waveform at a drain node of a main switch, the target number of valleys corresponding to a desired off-time of the main switch, the fractional valley controller modulating an off-time of the main switch between two or more modulated off-times. The target number of valleys corresponds to a non-integer number of valleys of the resonant waveform at the drain node of the main switch.

Each of the modulated off-times of the main switch corresponds to an integer number of valleys, and

the two or more modulated off-times of the main switch has an average value that corresponds to the desired off-time.

[007] Some embodiments described herein provide a power converter that includes a transformer having a primary winding configured to receive an input voltage, and a secondary winding configured to provide an output voltage to a load.

A main switch is coupled to the primary winding and configured to control a current through the primary winding to generate the output voltage. A resonant waveform at a drain node of the main switch includes one or more valleys during an off-time of the main switch. The power converter includes a primary side controller configured to control the main switch. The primary side controller includes a fractional valley controller configured to control the off-time of the main switch. The fractional valley controller is configured to determine a target number of valleys corresponding to a desired off-time of the main switch, the target number of valleys corresponding to a non-integer number of valleys. The fractional valley controller is configured to modulate the off-time of the main switch between two or more modulated off-times, each of the modulated off-times of the main switch corresponding to a respective integer number of valleys of the resonant waveform, and the two or more modulated off-times of the main switch has an average value that corresponds to the desired off- time.

BRIEF DESCRIPTION OF THE DRAWINGS

[008] FIG. 1 is a simplified schematic of a power converter that implements fractional valley switching, in accordance with some embodiments.

[009] FIG. 2 is a simplified schematic of the power converter of FIG. 1 configured as a fly-back converter, in accordance with some embodiments.

[0010] FIG. 3 is a simplified plot of signals related to the power converter shown in FIG. 2, in accordance with some embodiments.

[0011] FIG. 4 is a simplified schematic of a primary side controller of the power converter shown in FIG. 2, in accordance with some embodiments.

[0012] FIG. 5 is a simplified schematic of a fractional valley controller of the primary side controller shown in FIG. 4, in accordance with some embodiments.

[0013] FIGS. 6-7 are simplified schematics of valley integer modulators of the fractional valley controller shown in FIG. 5, in accordance with some embodiments.

[0014] FIGS. 8 is a simplified plot of signals related to the power converter shown in FIG. 2, in accordance with some embodiments.

[0015] FIGS. 9-10 are screenshots of experimental results for a test power converter that is similar to the power converter shown in FIG. 2, in accordance with some embodiments.

DETAIFED DESCRIPTION

[0016] Some embodiments described herein provide a fractional valley switching controller of a switch-mode power supply (“power converter”) that implements fractional valley switching during a quasi-resonant operating mode of the power converter. In some embodiments, the fractional valley switching controller (“fractional valley controller”) is part of a primary side controller of the power converter. In general, the power converter converts an input voltage on a primary side of a transformer to an output voltage on a secondary side of the transformer by controlling a current through a primary winding of the transformer using a primary side switch (“main switch”). During an off-time of the main switch, a resonant waveform develops at the drain node of the main switch. Based on the off-time of the main switch, the resonant waveform includes one or more peaks (local maxima) and one or more valleys (local minima). The primary side controller of the power converter is configured to control the off-time of the main switch such that the main switch is typically only switched when the drain-source voltage of the main switch is at a local minimum (i.e., at a valley of the resonant waveform). Unfortunately, in some instances, a total power to be delivered by the power converter can correspond to a non-integer number of valleys. Because a non-integer valley number does not correspond to a local minimum of the resonant waveform, switching the main switch at a non-integer valley number will result in switching losses that are greater than if the main switch is switched when the drain-source voltage is at a local minimum (i.e., corresponding to an integer number of valleys). The fractional valley switching controller disclosed herein advantageously controls, by fractional valley switching, the off-time of the main switch such that the main switch is typically only switched at integer valleys but enables the power converter to still deliver a total power that corresponds to a non-integer number of valleys. As is disclosed herein, such fractional valley switching is accomplished by the fractional valley controller by modulating a series of off-times of the main switch, each of the modulated off-times corresponding to a respective integer number of valleys. An average of the modulated off-times converges to an off-time that corresponds to a non-integer (i.e., fractional) valley. Thus, advantageously, a precise amount of power is delivered by the power converter, and switching losses are still minimized. Additionally, the fractional valley controller disclosed herein advantageously enables or disables fractional valley switching based on a switching cycle frequency of the main switch to prevent undesirable audible tones. Still further, the fractional valley controller disclosed herein provides for a fractional resolution of the non-integer number of valleys that is greater than that provided by typical valley dithering techniques.

[0017] FIG. 1 is a simplified circuit schematic of a power converter 100, in accordance with some embodiments. Some elements of the power converter 100 have been omitted from FIG. 1 to simplify the description of the power converter 100 but are understood to be present. In general, the power converter 100 includes an input voltage filter block 102, a rectifier block 104 (in the case of AC input), a quasi resonant converter circuit 106, a fractional valley controller 108 of a primary side controller 110 (a“power converter controller”), an output buffer circuit 111, a compensator/isolator (“feedback network”) 112, a signal difference block 114, an auxiliary winding 116 of a transformer 118 of the quasi-resonant converter circuit 106, an input voltage buffer capacitor Cl’, and a main switch Ml’, coupled as shown. Also shown is a drain-source voltage V _dsM r of the main switch M at a signal node 120, an input voltage Vi _n ’, a conditioned input voltage Vi _n at a signal node 122, an auxiliary voltage V _aUx , an output voltage V _out , an output current ii _oad, a feedback signal t _on , an error signal e _out , and a reference voltage V _ref .

[0018] The power converter 100 is configured to receive the input voltage Vi _n ’ and to provide the output voltage V _out and the output current ii _oad to a load RL based on an on-time and an off-time of the main switch M . The on-time and the off-time of the main switch MG are controlled by the primary side controller 110. The primary side controller 110 is configured to receive the input voltage V _m , the auxiliary voltage V _aUx , and a feedback signal (e.g., a magnetizing inductance charging time t _on , or other feedback signal) and to generate a main switch control signal PWM _MI’ to control the on-time and off-time of the main switch MG. In some embodiments, the quasi-resonant converter circuit 106 is implemented as a fly-back, forward, boost, or buck power converter.

[0019] FIG. 2 is a simplified circuit schematic of a power converter 200, in accordance with some embodiments. The power converter 200 is an example embodiment of the power converter 100 when the quasi-resonant converter circuit 106 is implemented as a fly-back converter. Some elements of the power converter 200 have been omitted from FIG. 2 to simplify the description of the power converter 200 but are understood to be present. In general, the power converter 200 includes an input voltage filter block 202, a rectifier block 204 (in the case of AC input), a fractional valley controller 208 of a primary side controller 210 (“a power converter controller”), an output buffer circuit 211, a compensator/isolator (“feedback network”) 212, a signal difference block 214, an auxiliary winding 216 of a transformer 218, a clamp circuit 232, a primary winding 234 of the transformer 218 on an input side of the power converter 200, a secondary winding 236 of the transformer 218 on an output side of the power converter 200, a synchronous switch controller 238, an input voltage buffer capacitor C l, a main switch Ml, and a synchronous switch M2, coupled as shown. Also shown is a drain-source voltage V _dsMi of the main switch Ml at a signal node 220, an input voltage V _m ’, a conditioned input voltage V _m at a signal node 222, an optional active clamp control signal AC _cti , an auxiliary voltage V _aux , an output voltage V _out , an output current ii _oad , a feedback signal (e.g., a magnetizing inductance charging time t _on , or other feedback signal), an error signal e _out , and a reference voltage V _ref . [0020] The power converter 200 is configured to receive the input voltage V _m ’ and to provide the output voltage V _out and the output current ii _oad to a load Abased on an on-time and an off-time of the main switch Ml. The on-time and the off-time of the main switch Ml are controlled by the primary side controller 210. The primary side controller 210 is configured to receive the input voltage V _m , an auxiliary voltage V _aux , and a magnetizing inductance charging time t _on (or other feedback signal) and to generate a main switch control signal PWM _MI to control the on-time and off-time of the main switch Ml.

[0021] The main switch Ml is coupled to the primary winding 234 and is configured to control a current through the primary winding 234 to charge a magnetizing inductance of the transformer 218 using the input voltage V _m during a first portion of a switching cycle of the power converter 200 (i.e., when the main switch Ml is turned on). The synchronous rectifier switch M2 controls a current through the secondary winding 236 to discharge the transformer 218 into the output buffer circuit 211 and the load R _L during a subsequent portion of the switching cycle (i.e., when the main switch Ml is turned off). The clamp circuit 232 limits the drain- source voltage VdsMi developed at the drain node of the main switch Ml to a voltage that is less than a maximum safe operating voltage of the main switch Ml. In some embodiments, the clamp circuit 232 is an active clamp circuit that is self-driven (e.g., the clamp circuit 232 does not require a control signal provided by the primary side controller 210). In other embodiments, the clamp circuit 232 is an active clamp circuit that is controlled by the primary side controller 210 using the optional active clamp control signal AC _cti . In still other embodiments, the clamp circuit 232 is a resistor-capacitor-diode (RCD) snubber circuit.

[0022] The feedback network 212 generates an internal error signal that is representative of a difference between the output voltage V _out at the output of the power converter 200 and the reference voltage V _ref . In some embodiments, the feedback network 212 processes the difference through an internal proportional- integral (PI) or proportional-integral-differential (PID) compensator. In some embodiments, the output from the feedback network 212 is mirrored from the output side of the power converter 200 to the input side of the power converter 200 using an isolator. The feedback network 212 provides a feedback signal to the primary side controller 210 which adjusts the main switch control signal PWM _MI based on the feedback signal. For example, in some embodiments, the feedback signal corresponds to a desired on-time t _on for the main switch Ml to charge the magnetizing inductance of the transformer 218.

[0023] The primary side controller 210 is configured to receive the feedback signal from the feedback network 212, the input voltage Vm, and the auxiliary voltage Vaux, and to generate the main switch control signal PWM _MI based on these received signals. The main switch control signal PWM _MI causes the main switch Ml to turn on and off in accordance with the on-time and an off-time t _off of the main switch Ml. During quasi-resonant operation of the power converter 200, when the main switch Ml is off, a resonant waveform develops at a drain node of the main switch Ml. The resonant waveform includes a series of voltage peaks (local maxima) and valleys (local minima). The primary side controller 210 advantageously controls the main switch Ml using the main switch control signal PWM _MI such that the main switch Ml is turned on when the voltage VdsMi is at a local minimum, i.e., at a valley of the resonant waveform. During a series of switching cycles of the main switch Ml, the fractional valley controller 208 modulates the valley at which the main switch Ml is turned on such that an average of the sequence of modulated valleys converges on a non-integer valley number. For example, an integer valley sequence of integer valley numbers: {2,2,2, 1 } has a non-integer (i.e., fractional) average value of 1.75.

[0024] A simplified plot 300 of the drain-source voltage VdsMi (i.e., a resonant waveform), at the drain node of the main switch Ml, having integer valleys 304a-c during a first switching cycle 306, and integer valleys 308a-b during a second switching cycle 310 is shown in FIG. 3. By adjusting the off-time of the main switch Ml, the primary side controller 210 adjusts a total power (iioad, V _ou t) delivered to the load RL. For example, by adjusting the off-time of the main switch Ml to switch on the third valley 304c of the first switching cycle 306, the primary side controller 210 will cause less power to be delivered to the load RL than during the second switching cycle 310 during which the main switch Ml is switched on the second valley 308b.

[0025] Unfortunately, in some instances, the total power to be delivered to the load R _L will correspond to a non-integer number of valleys (e.g., the point 312). As discussed previously, switching the main switch Ml when the drain-source voltage VdsMi of the main switch Ml is not at a minimum results in switching losses that are greater than if the main switch Ml is switched only when the drain-source voltage VdsMi is at a minimum (i.e., corresponding to an integer number of valleys). Thus, if the main switch Ml is frequently switched at a non-integer number of valleys (e.g., the point 312), switching losses of the power converter 200 will be greater than if the main switch Ml is switched at any of the integer number of valleys (e.g., 304a-c).

[0026] The fractional valley controller 208 as disclosed herein advantageously controls, by fractional valley switching, the off-time of the main switch Ml such that the main switch Ml is only switched at an integer number of valleys (i.e., in the middle of one of the valleys) but enables the power converter 200 to still deliver a total power to the load RL that corresponds to a non-integer number of valleys.

Additionally, fractional valley switching as disclosed herein enables such non-integer numbers of valleys to have a greater than typical fractional range. For example, a typical valley dithering approach that dithers or hops between two adjacent valleys may deliver a total power that corresponds to an average between the two adjacent valleys. That is, hopping or dithering between valley 1 (304a) and valley 2 (304b) will converge on an average that corresponds to valley 1.5. However, such typical valley dithering approaches cannot deliver a total power that corresponds to a greater resolution of decimal values between integer valleys (e.g., corresponding to valley 1.25, valley 1.3, valley 1.4, valley 1.45, valley 1.55, and so on).

[0027] Details of the primary side controller 210, in accordance with some embodiments, are shown in FIG. 4. Some elements and signals of the primary side controller 210 have been omitted from FIG. 4 to simplify the description of the primary side controller 210 but are understood to be present. In general, the primary side controller 210 includes a PWM ramp generator (“PWM Ramp Gen.”) 402, an analog to digital converter (ADC) module 404, a power optimization controller 406, a fractional valley controller 408, a zero-crossing detector (ZCD) 410, and other modules 412, coupled as shown. In some embodiments, the other modules 412 include other digital and/or analog modules of the primary side controller 210, such as additional control circuitry, one or more processors (e.g., microcontrollers, microprocessors, DSPs, ASICs, FPGAs), volatile data storage, non-volatile data storage, communication modules, or still other components. In some embodiments, one or more components of the other modules 412 may be in signal communication with one or more of the described components of the primary side controller 210 and/or with other components of the power converter 200.

[0028] The ADC module 404 is configured to generate a digitized feedback signal t _on (n) based on the feedback signal t _on (the desired on-time of the main switch Ml). The ADC module 404 is further configured to generate a digitized input voltage Vin(n) based on the conditioned input voltage Vi _n . In some embodiments, the power optimization controller 406 generates a desired off time t _0ff ^* (n) of the main switch Ml as described in related application, U.S. Patent Application No. 16/020,496. The ZCD 410 generates a valley detection signal valley _det for each detected valley (e.g., the valleys 304a-c). In some embodiments, the ZCD 410 detects each of the valleys of the resonant waveform at the drain node of the main switch Ml using the auxiliary voltage V _aux generated using the auxiliary winding 216. In other embodiments, the ZCD 410 detects each of the valleys of the resonant waveform at the drain node of the main switch Ml using a voltage received from, or based on the voltage at, the drain node of the main switch Ml. The fractional valley controller 408 is configured to receive the valley detection signal valley _det , a measured off-time t _0ff (n) of the main switch Ml, a switching cycle frequency signal t _sw (n) (a value representative of the switching period or switching frequency of the main switch Ml), and a desired off- time t _0ff ^* (n) for the main switch Ml from the power optimization controller 406. The desired off-time t _0ff ^* (n) is a calculated off-time of the main switch Ml which corresponds to a total power to be delivered to the load RL. AS described earlier, in some instances the desired off-time t _0ff ^* (n) of the main switch Ml corresponds to a non-integer number of valleys. The fractional valley controller 408 is configured to modulate the off-time t _0ff (n) of the main switch Ml between a series of modulated off- times. A modulated off-time is an off-time of the main switch Ml that differs in time as compared to one or more other off-times in the series of modulated off-times. That is, in the series of modulated off-times, a first modulated off-time may have a duration of t, a second modulated off-time may have a duration of t + t, a third modulated off- time may also have a duration of t + t, a fourth modulated off-time may have a duration of t..., and so on, where t is a delay.

[0029] Each of the modulated off-times corresponds to an integer number of valleys of the resonant waveform at the drain node of the main switch Ml. However, an average value of the modulated off-times of the main switch Ml converges to an average off-time of the main switch Ml that corresponds to a non-integer number of valleys. Thus, the fractional valley controller 408 advantageously switches the main switch Ml at points where the drain-source voltage V _d sMi of the main switch Ml is minimized, but the total power delivered to the load R _L is equal to a total power that corresponds to a non-integer number of valleys. The fractional valley controller 408 causes the main switch Ml to switch in accordance with the modulated off-times of the main switch Ml by transmitting a reset signal, PWM _reset , to the PWM ramp generator 402 when a number of valleys detected using the ZCD 410 exceeds a target number of valleys determined by the fractional valley controller 408.

[0030] A simplified schematic of the fractional valley controller 408, in accordance with some embodiments, is shown in FIG. 5. Some elements of the fractional valley controller 408 have been omitted from FIG. 5 to simplify the description of the fractional valley controller 408 but are understood to be present. In general, the fractional valley controller 408 includes an OR gate 502, a valley counter 504, an audible noise filter 506, a first signal comparison block 508, a second signal comparison block 510, a valley integer modulator 512, and a target valley generator 514. The audible noise filter 506 generally includes a third signal comparison block 516.

[0031] The first signal comparison block 508 is configured to receive the measured off-time t _0ff (n) of the main switch Ml and the desired off-time _f ^* (n) of the main switch Ml and to generate an off-time adjustment signal (“Incr./Dec.”). The first signal comparison block 508 compares the measured off-time t _0ff (n) to the desired off-time _f ^* (n). If the measured off-time t _0ff (n) is greater than the desired off- time t _0ff ^* (n), the first signal comparison block 508 generates a decrement off-time adjustment signal which indicates that the main switch Ml should be switched at a point in time that corresponds to an earlier valley than that at which the main switch Ml is currently being switched. If the measured off-time t _0ff (n) is not greater than the desired off-time _f ^* (n), the first signal comparison block 508 generates an increment off-time adjustment signal which indicates that the main switch Ml should be switched at a point in time that corresponds to a later valley than that at which the main switch Ml is currently being switched.

[0032] The target valley generator 514 receives the off-time adjustment signals (“Incr./Dec.”) from the first signal comparison block 508 and generates a target valley number, valley ^* (n _mt , n _de c), having an integer portion (i.e., n _mt ) and a decimal portion (i.e., n _dec ). For instance, if the target valley number is 2.65, the integer portion corresponds to the integer value 2, and the decimal portion

corresponds to the decimal value 0.65. However, the target valley number is not limited to only corresponding to non-integer numbers of valleys. For example, for some desired off-times Vf*(n) of the main switch Ml, the target valley number may have a decimal portion that is equal to zero. [0033] The valley integer modulator 512 is configured to receive the target valley number, valley ^* (n _mt , n _dec ), and to generate a series of modulated integer valley numbers valley ^* (n). A modulated integer valley number is a valley number that differs in number as compared to one or more other valley numbers in the series of modulated integer valley numbers. That is, in the series of modulated integer valley numbers, a first modulated integer valley number may be i, a second modulated integer valley number may be 2, a third modulated integer valley number may also be 2, a fourth modulated valley integer number may b e l ..., and so on. Advantageously, in some embodiments, the valley integer modulator 512 is configured to generate non- alternating sequences of modulated integer valley numbers. An example of an alternating sequence of integer valley numbers is { 1, 2, 1, 2, 1, 2,... }. An example of a non-altemating sequence of integer valley numbers is { 1, 2, 2, 2, 1, 2, 2, 2,... }.

That is, the fractional valley controller 208 is configured to generate a first sequence of one or more first integer valley numbers in series immediately followed by a second sequence of one or more second integer valley numbers in series, where a length of the first sequence is different than a length of the second sequence, and the one or more first integer valley numbers are not equal to the one or more second integer valley numbers.

[0034] Each of the modulated integer valley numbers valley ^* (n) corresponds to a modulated off-time of the main switch Ml. Thus, the series of modulated integer valley numbers, valley ^* (n), converge on an average valley number that is equal to, or close to equal to (i.e.,“about”), the target valley number which is a non-integer valley number.

[0035] The valley counter 504 receives the valley _det signal from the ZCD 410 and increments an internal counter to generate a detected valley count, valley(n). The second signal comparison block 510 compares a most recent detected valley count, valley(n), to a most recent modulated integer valley number, valley ^* (n). Upon determining that the most recent detected valley count, valley(n), is greater than the most recent modulated integer valley number, valley ^* (n), the second signal comparison block 510 transmits a PWM _reset signal to the OR gate 502 and to the PWM ramp generator 402. Upon receiving the PWM _reset signal, the PWM ramp generator 402 transmits a main switch control signal PWM _M I at a level that enables the main switch Ml. Thus, the main switch Ml is advantageously switched at a point in time that corresponds to an integer valley number even though the output power of the power converter 200 converges to a power corresponding to a non-integer valley number.

[0036] The OR gate 502 transmits a reset signal to the valley counter 504 upon receiving the PWM _reset signal. Upon receiving the reset signal, the valley counter 504 resets the internal valley count value to an initial value (e.g., 0).

Additionally, the OR gate 502 transmits the reset signal to the valley counter 504 upon receiving a blanking signal (e.g., during a time when the main switch Ml is not disabled).

[0037] The valley integer modulator 512 is advantageously configured to only perform fractional valley switching when a switching frequency of the main switch Ml is higher than a minimum frequency threshold such that the modulated off-times of the main switch Ml will not generate frequencies that are in the range of audible noise (e.g., equal to or less than 30kHz). The audible noise filter 506 receives the measured switching cycle frequency signal t _sw (n) from the PWM ramp generator 402 and receives a minimum switching cycle frequency threshold t _min (n) (e.g., from a processor or other component of the other modules 412, or from another source such as a configuration component of the power converter 200). Upon determining that the measured switching cycle frequency signal t _sw (n) is less than the minimum switching cycle frequency threshold t _mm (n), the third signal comparison block 516 sends a de- asserted fractional _en signal to the valley integer modulator 512 to disable fractional valley switching. Upon determining that the measured switching cycle frequency signal t _sw (n) is not less than the minimum switching cycle frequency threshold t _min (n), the third signal comparison block 516 sends an asserted fractional _en signal to the valley integer modulator 512 to enable fractional valley switching. Thus, fractional valley switching is advantageously disabled if fractional valley switching would result in undesirable audible tones.

[0038] FIG. 6 is a simplified schematic of an example valley integer modulator 612 that implements the valley integer modulator 512, in accordance with some embodiments. The valley integer modulator 612 is suitable for switching cycle frequencies t _sw (n) that are greater than 60kHz due to generated tones which are in some instances one-half of the switching cycle frequency t _sw (n). Some elements of the valley integer modulator 612 have been omitted from FIG. 6 to simplify the description of the valley integer modulator 612 but are understood to be present. The valley integer modulator 612 generally includes a mux 602 (i.e., a component that receives two or more input signals and selectively passes one of the two or more input signals to an output of the mux), a first modulator 604, a second modulator 606, and a signal adder block 608. The mux 602 receives the fractional _en signal from the audible noise filter 506. If the fractional _en signal is de-asserted, the mux 602 passes an output from the first modulator 604 to the signal adder block 608. If the fractional _en signal is asserted, the mux 602 passes an output from the second modulator 606 to the signal adder block 608. In some embodiments, the first modulator 604 generates an output with hysteresis such that the output, inc, of the mux 602 transitions to 1 if the decimal portion, valley ^* (n _dec ), is greater than or equal to 0.75 for a given initial output of 0. In such embodiments, the first modulator 604 generates an output with hysteresis generally such that the output, inc, of the mux 602 transitions to 0 if the decimal portion, valley ^* (n _dec ), is less than or equal to 0.25 for a given initial output of 1.

When fractional valley switching is disabled, output ripple of the power converter 200 may increase as compared to output ripple when fractional valley switching is enabled.

[0039] In some embodiments, the second modulator 606 generates an output using a different hysteresis than that of the first modulator 604. In such embodiments, the second modulator 606 generates an output that modulates between 1 and 0 based the decimal portion, v alley *(ndec) of the target valley number, valley ^* (n _mt , ndec). That is, for a range of decimal values that, in contrast, corresponds to a dead-hand of the first modulator 604, the second modulator 606 generates a stream of values that modulate between 0 and 1.

[0040] The output, inc, of the mux 602 is summed with the integer portion valley ^* (n _mt ) of the target valley number valley ^* (n _mt , n _dec ) by the signal adder block 608, thereby generating the stream of modulated output valley numbers, valley ^* (n).

[0041] FIG. 7 is a simplified schematic of another example valley integer modulator 712 that implements the valley integer modulator 512, in accordance with some embodiments. The valley integer modulator 712 is suitable for switching cycle frequencies t _sw (n) that are greater than 250kHz due to low-frequency tones that are generated in some instances by a k ^Lh -ordcr sigma-delta modulator implemented by a second modulator 706. Some elements of the valley integer modulator 712 have been omitted from FIG. 7 to simplify the description of the valley integer modulator 712 but are understood to be present. The valley integer modulator 712 generally includes a mux 702, a first modulator 704, the second modulator 706, and a signal adder block 708. The mux 702 receives the fractional _en signal from the audible noise filter 506. If the fractional _en signal is de-asserted, the mux 702 generates an output, inc, using an output from the first modulator 704. The output, inc, for the mux 702 is received by the signal adder block 708. If the fractional _en signal is asserted, the mux 702 generates the output, inc, using an output from the second modulator 706. In some embodiments, the first modulator 704 generates an output as described with reference to the first modulator 604 of FIG. 6.

[0042] The k ^Lh -ordcr sigma-delta modulator implemented by the second modulator 706 is configured to receive the decimal portion, valley ^* (n _dec ) of the target valley number valley ^* (n _mt , n _dec ) and to generate an output stream of“highs” and “lows” (i.e., l’s and 0’s) based on the decimal portion, valley ^* (n _dec ). The sigma-delta modulator of the second modulator 706 generates an output stream of values such that a number of l’s in the output stream of values increases as a value of the decimal portion, valley ^* (n _dec ) increases. Similarly, the sigma-delta modulator of the second modulator 706 generates an output stream of values such that a number of 0’s in the output stream of values increases as a value of the decimal portion, valley ^* (n _dec ) decreases. The order of the sigma-delta modulator of the second modulator 706 dictates the number of integrators, i.e., the number of feedback loops, utilized. The higher the order, the higher the achievable fractional valley resolution. The sigma- delta modulator of the second modulator 706 advantageously generates the output stream as a noise-shaped signal to achieve higher resolution of fractional valley switching with a predictive frequency content as compared to hysteresis-based approaches. For example, an example sequence of modulated integer valley numbers, valley ^* (n), generated by the valley integer modulated 712 could include a sequence such as {4, 2, 1, 2... } which converges on a non-integer valley number of 2.25.

[0043] FIG. 8 shows a simplified plot 800 of signals related to the power converter 200 indicating operation thereof, in accordance with some embodiments. The simplified plot 800 includes a plot 802 of the drain-source voltage VdsMi of the main switch Ml (i.e., a resonant waveform), a plot 804 of the integer portion valley ^* (n _mt ) of the target valley number, valley ^* (n _mt , n _dec ), a plot 806 of the output, inc, of the mux 602 or 702, and a plot 808 of a resultant modulated valley number, valley ^* (n). In the example shown in the simplified plot 800, an average valley number of the resonant waveform at the drain node of the main switch Ml converges on a non-integer valley number of 2.5. [0044] FIG. 9 shows screenshots 902, 904 of experimental results for a test power converter that is similar to the power converter 200, in accordance with some embodiments. Each of the screenshots 902, 904 show a drain-source voltage VdsMi measurement of a main switch of the test power converter over time. The screenshot 902 illustrates fractional valley switching between a I ^st valley and 2 ^nd valley to achieve a 1.5A output to a load of the test power converter. The screenshot 904 illustrates fractional valley switching between a 4 ^th valley and a 5 ^th valley to achieve a 0.75 A output to the load of the test power converter.

[0045] FIG. 10 shows screenshots 1002, 1004 of experimental results for a test power converter that is similar to the power converter 200, in accordance with some embodiments. Each of the screenshots 1002, 1004 show time (1002a/ 1004a) and frequency domain (l002b/l004b) measurements of a drain-source voltage VdsMi of a main switch of the test power converter. The screenshot 1002 illustrates the time and frequency domain measurements of VdsMi when fractional valley switching is enabled (i.e., fractional _en =1), and the screenshot 1004 illustrates the time and frequency domain measurements of VdsMi when fractional valley switching is disabled (i.e., fractional _en = 0) for a 90Vac/5. lVdc 1.5A operating condition of the test power converter. As shown, the output voltage ripple of the test power converter is advantageously reduced from 340mV to 260mV when fractional valley switching is enabled. A 60kHz frequency component is generated by the test power converter when fractional valley switching is enabled, however, the 60kHz frequency component is outside of an audible noise range.

[0046] Reference has been made in detail to embodiments of the disclosed invention, one or more examples of which have been illustrated in the accompanying figures. Each example has been provided by way of explanation of the present technology, not as a limitation of the present technology. In fact, while the specification has been described in detail with respect to specific embodiments of the invention, it will be appreciated that those skilled in the art, upon attaining an understanding of the foregoing, may readily conceive of alterations to, variations of, and equivalents to these embodiments. For instance, features illustrated or described as part of one embodiment may be used with another embodiment to yield a still further embodiment. Thus, it is intended that the present subject matter covers all such modifications and variations within the scope of the appended claims and their equivalents. These and other modifications and variations to the present invention may be practiced by those of ordinary skill in the art, without departing from the scope of the present invention, which is more particularly set forth in the appended claims. Furthermore, those of ordinary skill in the art will appreciate that the foregoing description is by way of example only, and is not intended to limit the invention.