Title:
FRAME MEMORY CONTROL CIRCUIT, DISPLAY DEVICE AND FRAME MEMORY CONTROL METHOD
Document Type and Number:
WIPO Patent Application WO/2013/164947
Kind Code:
A1
Abstract:
This frame memory control circuit is provided with: a separation circuit which separates frame-by-frame image data inputted in synchronization with a first synchronization signal into a plurality of subfields; a frame memory which has a plurality of blocks, image data of any of the subfields being written into each of the blocks; a read control circuit which reads image data written in the blocks designated in a predetermined order such that image data corresponding to one frame is read in synchronization with a second synchronization signal having the same cycle as the first synchronization signal and delayed by a predetermined time; and a write control circuit which, when the image data is read from one of the blocks by the read control circuit, writes image data separated into respective subfields by the separation circuit into the one block.
Inventors:
KUMETA MASAYUKI (JP)
ISHII RYO (JP)
MATSUMOTO KAZUHIRO (JP)
YAMASHITA SHINJI (JP)
LEE ANSU (KR)
ISHII RYO (JP)
MATSUMOTO KAZUHIRO (JP)
YAMASHITA SHINJI (JP)
LEE ANSU (KR)
Application Number:
PCT/JP2013/061259
Publication Date:
November 07, 2013
Filing Date:
April 16, 2013
Export Citation:
Assignee:
SAMSUNG DISPLAY CO LTD (KR)
International Classes:
G09G3/36; G09G3/20; G09G3/28; G09G5/00
Foreign References:
| JPH0421188A | 1992-01-24 | |||
| JPH06301590A | 1994-10-28 | |||
| JPH11313248A | 1999-11-09 | |||
| JP2002281460A | 2002-09-27 | |||
| JP2006072311A | 2006-03-16 | |||
| JP2002304149A | 2002-10-18 | |||
| JPH08211846A | 1996-08-20 |
Attorney, Agent or Firm:
Takahashi, Hayashi and Partner Patent Attorneys, Inc. (JP)
Patent business corporation Takahashi and wood and partners (JP)
Patent business corporation Takahashi and wood and partners (JP)
Download PDF: