Title:
FREQUENCY DIVIDER WITH VARIABLE DIVISION RATE
Document Type and Number:
WIPO Patent Application WO2004084411
Kind Code:
A8
Abstract:
The invention relates to a frequency divider with variable division rate, which is made using CMOS technology. The inventive divider comprises a plurality of cells (c1 to c3) which are mounted in a chain, the output of the last cell of the chain being fed back (7) to the input of the first cell. Each cell comprises an inverter (3), the transition of which can be authorised or inhibited by control transistors (M1, M4) which are mounted in series with the inverter circuit (3) between the positive and negative power terminals (1, 2). The signal with the frequency to be divided (CK) is applied to the gates of the aforementioned transistors (M1, M4). The divided frequency signal is supplied at the output (8) of the last cell of the chain of cells (c1 to c3). According to the invention, in one (c2) of the cells in the chain of cells, one (M4) of the transistors (M1, M4) with one type of conductivity (n) is connected in parallel to a short-circuit transistor (M5) with the same type of conductivity. Moreover, the gate of the short-circuit transistor (M5) is connected such that it can be rendered conductive by a division rate change control signal (MC).
Inventors:
RUFFIEUX DAVID (CH)
Application Number:
PCT/CH2004/000120
Publication Date:
December 01, 2005
Filing Date:
March 03, 2004
Export Citation:
Assignee:
SUISSE ELECTRONIQUE MICROTECH (CH)
RUFFIEUX DAVID (CH)
RUFFIEUX DAVID (CH)
International Classes:
H03K23/54; H03K23/66; H03L7/193; (IPC1-7): H03K23/40; H03K21/00; H03L7/18
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