| US5260608A | 1993-11-09 | |||
| US5463337A | 1995-10-31 | |||
| US5514990A | 1996-05-07 | |||
| US5120989A | 1992-06-09 | |||
| US5600273A | 1997-02-04 |
| 1. | A frequency multiplier for producing an output signal having a frequency that is a multiple of frequency of an input periodic reference signal, the frequency multiplier comprising: delay means for successively phase shifting said reference signal by an amount controlled by an input control signal to produce a set of periodic tap signals; phase control means receiving said reference signal and one of said tap signals and producing said control signal supplied as input to said delay meanε, said phase control means adjusting said control signal such that said one tap signal is phase locked to said reference signal; and logic means receiving at least two of said tap signals and producing said output signal aε a logical combination of said tap signals . |
| 2. | The frequency multiplier in accordance with claim 1 0 wherein said logic means comprises an exclusive OR (XOR) gate. |
| 3. | The frequency multiplier in accordance with claim 1 wherein said delay means comprises a plurality of substantially similar logic circuits, each producing an output 5 signal in delayed response to an input signal with a delay being adjusted response to said control signal supplied to each stage, the logic circuits being connected in series with a first logic circuit of the series receiving the reference signal as input, each logic circuit of the series other than D the first logic circuit receiving an output signal of a preceding logic circuit of the series as input. |
| 4. | The frequency multiplier in accordance with claim 3 wherein each of said logic circuits consists of an inverter 5 circuit. |
| 5. | A frequency multiplier for producing an output signal having a frequency that is a multiple of a frequency of an input periodic reference signal, the frequency multiplier comprising: a set of inverters connected in serieε for successively delaying an input periodic reference signal to produce a set of inverter output signals, phase controller means linked to said inverters for adjusting the inverters switching speed so that an output signal of a last inverter of the serieε iε phase locked to the reference signal, and an XOR gate for logically combining a pair of said inverter output signals to produce a periodic output signal of frequency which is a multiple of a frequency of the reference signal . |
| 6. | A frequency multiplier for producing an output signal having a frequency that is a multiple of a frequency of an input periodic reference signal, the frequency multiplier comprising: a plurality of substantially similar logic circuits, each producing an output signal in delayed response to an input signal with a delay being adjusted response to said control signal supplied to each stage, the logic circuits being connected in series with a first logic circuit of the series receiving the reference signal as input, each logic circuit of the series other than the first logic circuit receiving an output signal of a preceding logic circuit of the series as input; phase control means for receiving said reference signal and an output signal produced by one of said logic circuits, and for producing said control signal supplied aε input to said logic circuits, said phase control means adjusting said control signal such that the output signal of said one logic circuit iε phase locked to said reference signal; and an XOR gate receiving two of εaid tap εignalε and producing said output signal as a logical combination of said tap signalε. |
Background of the Invention Field of the Invention The present invention relates in general to frequency multipliers and in particular to a frequency multiplier producing output signals by logically combining taps of a delay locked loop.
Description of Related Art
A frequency multiplier produces an output signal of frequency that is a multiple of a reference signal's frequency. FIG. 3 illustrates a common prior art frequency multiplier employing a ring oscillator 100 formed by a set of inverters 110 connected end-to-end to form a loop. A signal pulse circulates through ring oscillator 100 with a frequency proportional to the switching speed of inverters 110. A phase comparator 120 receives an input reference signal A and the output B of a counter 130. Counter 130 counts pulses of an oscillator output signal C appearing at the output of one of inverters 110 and pulses its output signal B after every Nth pulse of the inverter output signal C. Phase comparator 120 drives its output signal D high when signal B lags signal A and drives its output signal D low when signal A lags signal B. A loop filter 140 integrates the comparator output signal D to produce a signal E supplying power to inverters 110. The switching speed of inverters 110, and therefore the frequency of signal C, increases with the magnitude of signal E. Feedback provided by comparator 120, counter 130 and filter 140 adjusts the magnitude of supply signal E so that the frequency of oscillator output signal C is N times that of the input reference signal A. One problem with this circuit is phase jitter, a second order oscillation in frequency of the oscillator output signal C.
Summary of the Invention A frequency multiplier in accordance with the present invention includes a set of substantially identical inverters connected in series for successively delaying an input periodic reference signal to produce a set of inverter output signals. A phase controller adjusts the delay provided by each inverter so that the output signal of a last inverter of the series is phase locked to a reference signal supplied aε input to the first inverter of the series. Thus the inverter outputs are evenly distributed in phase with pulse edges evenly dividing the period of the reference signal. A set of XOR gates logically combine selected inverter output signals to produce periodic output signals of frequencies which are even multiples of the reference signal . It is accordingly an object of the invention to provide a frequency multiplier for producing an output signal having a frequency that is a multiple of the frequency of an input reference signal .
The concluding portion of this specification particularly points out and distinctly claims the subject matter of tiie present invention. However those skilled in the art will best understand both the organization and method of operation of the invention, together with further advantages and objects thereof, by reading the remaining portions of the - specification in view of the accompanying drawing(s) wherein like reference characters refer to like elements.
Brief Description of the Drawing(s) FIG. 1 is a block diagram illustrating a frequency multiplier in accordance with the present invention,
FIG. 2 is a timing diagram illustrating operation of the frequency multiplier of FIG. 1; and
FIG. 3 is a block diagram of a prior art frequency multiplier.
Description of the Preferred Embodiment(s) FIG. 1 illustrates a frequency multiplier 10 in accordance with the present invention. Frequency multiplier 10 includes a variable delay line 12 formed by a set of eight identical logic elements (suitably inverters) G1-G8, a phase comparator 14 and a loop filter 16. Inverters G1-G8 are connected in series and produce a set of eight output tap signals T1-T8 progressively shifted in phase from a periodic reference TO supplied as input to the first inverter GI of the series. The amount of delay provided by each inverter stage is determined by a control signal VDLL supplying power to inverters G1-G8. Since the magnitude of VDLL controls the rate at which a pulse of the TO signal propagates through inverters G1-G8 to the input of phase comparator 14, the VDLL signal controls the amount of phase shift provided by each inverter stage. The TO reference signal and the tap signal output T8 of the last inverter G8 of the series provide inputs to phase comparator 14. The loop filter 16 integrates an output signal COMP produced by phase comparator 14 and supplies its resulting output signal as the control signal
VDDL input to inverters G1-G8. Phase comparator 14 drives its output signal COMP high when tap T8 lags the TO reference signal and drives its output signal COMP low when the TO reference signal lags tap T8. Feedback provided by phase comparator 14 and filter 16 adjusts the magnitude of VDLL to phase lock tap T8 to the TO reference signal. Thus, as illustrated by the timing diagram of FIG. 2, all tap signals T1-T8 share the frequency of the input reference signal TO, but each tap signal TN (for N = 1 to 7) is shifted in phase from the reference signal TO by N/8ths of a cycle. The TO reference and T8 tap signals are represented in FIG . 2 by the same waveform because tap signal T8 is phase locked to the TO reference signal.
Referring to FIGS. 1 and 2, frequency multiplier 10 also includes a set of exclusive OR (XOR) gates X1-X3. XOR gate XI receives the TO reference signal and the T2 output signal aε its inputs and produces a multiplier output signal Al . With
T2 1/4 cycle out of phase with the TO reference signal, the A l output signal has a frequency twice that of TO . XOR gate X2 receives taps Tl and T3 as its inputs and produces a multiplier output signal A2 also having a frequency twice that of TO but shifted in phase from Al by 1/4 cycle. The A l and A2 signals provide inputs to XOR gate X3 producing an output signal A3. Since A2 is 1/4 cycle out of phase with Al, output signal A3 has a frequency twice that of Al and A2 and four times that of the TO signal. Thus frequency multiplier 10 produces output signals of frequency two and four times that of the input reference signal TO. The output signals exhibit little jitter because the feedback provided by comparator 14 and filter 16 tightly couples the tap signals T1-T8 to TO.
The frequency multiplier circuit of the present invention could produce frequency multiplied output signals having other than 50% duty cycle when we choose other combinations of tap signals as XOR gate inputs. For example, if we choose taps Tl and T2 as an input to an XOR gate, the output of that XOR gate would also be twice the frequency of the reference signal TO but would have a 25% duty cycle.
When we increase the number of inverter stages in the delay line and number of levels of XOR gates we can increase the range of frequency multiplication. For example a frequency multiplier having 16 inverter stages producing sixteen output tap signals T1-T16 and employing seven XOR gates X1-X7 interconnected in a hierarchical manner produces output signals of frequencies 2, 4 and 8 times that of TO. Suitable interconnections for such a multiplier are listed below in Table I.
TABLE I
The first line of Table I indicates that XOR gate XI has delay signals TO and T4 as its inputs and would produces an output signal Al of frequency twice that of TO. The last line of Table I indicates XOR gate X7 receives output signals A3 and A4 of XOR gates X5 and X6 and produces an output signal A7 having a frequency eighth times that of TO . In general a frequency multiplier with a tapped delay line having 2 N inverter stages and a hierarchy of N! suitably interconnected XOR gates can produce a set of output signals having frequencies that are power of two multiples of the input reference signal TO belonging to the set {2, 4 ... 2 N_1 } .
It should be understood that the function of inverter stages G1-G8 could be implemented by other types of adjustable delay elements such as buffers or logic gates. The inverter stages and XOR gates may also be implemented by differential logic elements. Thus, while the foregoing specification has described preferred embodiment (s) of the present invention, one skilled in the art may make many modifications to the preferred embodiment without departing from the invention in its broader aspects. The appended claims therefore are intended to cover all such modifications as fall within the true scope and spirit of the invention.