Title:
FREQUENCY SYNTHESIZER AND TIME-TO-DIGITAL CONVERTER
Document Type and Number:
WIPO Patent Application WO/2012/066700
Kind Code:
A1
Abstract:
A frequency synthesizer is provided with an oscillator (1), and a TDC circuit (7) for detecting a normalized phase difference between a frequency-divided signal (CKV) of the oscillator (1) output and a reference signal (Fref), and controls the frequency of the oscillator (1) on the basis of the normalized phase difference detected by the TDC circuit (7). The TDC circuit (7) is provided with a second oscillator (711), and a counter (712) for counting the periodicity of the output signal (OSC2) of the second oscillator (711), and obtains, from the output of the counter (712), a count value equivalent to the cycle of the frequency-divided signal (CKV), and a count value equivalent to the phase difference between the frequency-divided signal (CKV) and the reference signal (Fref), to calculates the normalized phase difference on the basis of those count values.
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Inventors:
OHARA ATSUSHI
Application Number:
PCT/JP2011/003973
Publication Date:
May 24, 2012
Filing Date:
July 11, 2011
Export Citation:
Assignee:
PANASONIC CORP (JP)
OHARA ATSUSHI
OHARA ATSUSHI
International Classes:
H03L7/085; H03K5/26; H03L7/06
Domestic Patent References:
| WO2010032830A1 | 2010-03-25 |
Foreign References:
| JP2010273118A | 2010-12-02 |
Other References:
DONDI, S. ET AL.: "High-Level Design Flow for All-Digital PLLs", 24TH IEEE NORCHIP CONFERENCE, 2006., November 2006 (2006-11-01), pages 247 - 250, XP031057894
Attorney, Agent or Firm:
MAEDA, Hiroshi et al. (JP)
Hiroshi Maeda (JP)
Hiroshi Maeda (JP)
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Claims: