Title:
FREQUENCY SYNTHESIZER
Document Type and Number:
WIPO Patent Application WO/2012/150621
Kind Code:
A1
Abstract:
A frequency synthesizer according to the present invention is provided with a decimal part data output unit (10) which generates two values for decimal part data (F, F+1) and outputs either one of the generated two values by switching based on a desired division ratio, a decimal part control circuit (5) which performs delta‐sigma modulation for the decimal part data from said decimal part data output unit and outputs a decimal part data after the delta‐sigma modulation, and an adder (6) which adds the decimal part data output from said decimal part control circuit to the input integer part data (M) and outputs the added result data to a variable frequency divider (2) as control data.
Inventors:
FUJITA MAYUKO
OCHIAI MINORU
OCHIAI MINORU
Application Number:
PCT/JP2011/006147
Publication Date:
November 08, 2012
Filing Date:
November 02, 2011
Export Citation:
Assignee:
PANASONIC CORP (JP)
FUJITA MAYUKO
OCHIAI MINORU
FUJITA MAYUKO
OCHIAI MINORU
International Classes:
H03L7/197; H03K23/64; H03K23/68; H03L7/183; H03M3/02
Foreign References:
| JP2002152044A | 2002-05-24 | |||
| JPH09261048A | 1997-10-03 | |||
| US5986512A | 1999-11-16 |
Attorney, Agent or Firm:
NAKAJIMA, Shiro et al. (JP)
Shiro Nakajima (JP)
Shiro Nakajima (JP)
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