TECHNICAL FIELD

[0001] This disclosure relates generally to fully Differential Symmetrical High Speed Static CMOS Flip Flops and more particularly to fully Differential Symmetrical High Speed Static CMOS Flip Flop having Low Latency.

BACKGROUND

[0002] As is known in the art, one type of flip flop is a D-type flip-flop. A D-type flip flop stores the binary state of an input logic signal (D) at the moment of a positive edge of a clock pulse is applied to the D-type flip-flop at a clock pin (or negative edge if the clock pulse is active falling edge) and delays the state of D by one clock cycle. That is why it is commonly known as a delay-type flip flop. The D Flip-Flop can be interpreted as a delay line or zero order hold. With a D-type flip-flop, the signal on the D input is captured the moment the flip-flop is clocked, and subsequent changes on the D input will be ignored until the next clock edge event. One D-type flip-flop circuit is shown in FIG. 1.

[0003] As is also known in the art, one type of D-type flip flop circuit is fed both the true

(D) and complement (false) (D ) of the input signal. This type of flip-flop is sometimes referred to as a differential flip-flop circuit. With a differential flip-flop circuit, it is desirable that the circuit provides substantially equal transmission time for both the true and complementary data and has minimum transmission latency. Today, typical CMOS clock to output (Q) latency can be as high as 250ps in the more standard architectures. More particularly, the latency is process dependent with the smaller the gate channel length the smaller the latency; for example, a 0.5um gate width processes has latency on the order of Ins and a 0.18 um gate channel length having a latency of 250ps. There exist other architectures that can reduce this latency by approximately half but typical at the cost of imbalances in the time delay between the true and complementary data (sometimes referred to as asymmetrical switch points in the flip-flop circuit). [0004] As is also known in the art, one type of high speed flip flop is a dynamic gated CMOS inverter flip flop circuit, as distinguished from a static or latching type flip-flop circuit. This dynamic device stores the logic state of the data as a charge in the gate storage node region of a CMOS transistor of the circuit. However, the charge may suffer from leakage over time at the storage node and therefore the charge must be refreshed. Also since the storage is sample and held voltage on parasitic capacitance at the node, the charge susceptible to cross talk and noise of other related switching circuits.

SUMMARY

[0005] In accordance with the present disclosure, a flip-flop circuit is provided. The circuit is fed by a true logic signal and the complement of the true logic signal. The circuit includes a first logic signal storage circuit having a first input terminal fed by the true logic signal and a second input terminal fed by the complement of the true logic signal, the first logic signal storage circuit having a pair of output terminals. The circuit includes a second logic signal storage circuit having a pair of input terminals coupled to the pair of output terminals of the first logic signal storage circuit. In response to one of the clock signals: the first logic signal storage circuit passes the true and complement logic signals fed thereto for storage in the first logic signal storage circuit while the second logic signal storage circuit prevents the true and complement logic signals stored in the first logic signal storage circuit from passing from the pair of outputs of the first logic signal storage to the second storage circuit. In response to a subsequent one of the clock signals; the first logic storage circuit prevents the true and complement logic signals fed thereto from passing for storage in the first storage circuit while the second storage circuit passes the true and complement logic signals stored in the first storage circuit at the pair of outputs of the first storage circuit to the second storage circuit for storage in the second storage circuit.

[0006] In one embodiment, the true and complement logic signals stored in the first logic signal storage circuit are produced at the pair of outputs of the first logic signal storage circuit and the true and complement logic signals stored in the second logic signal storage circuit are produced at a pair of outputs of the second logic signal storage circuit. [0007] In one embodiment, the time delay between a time the true logic signal passes from the first input terminal to a first one of the pair of outputs of the second logic signal storage circuit is equal to the time delay between the time the complement of the true logic signal passes from the second input to a second one of the pair of outputs of the second logic signal storage circuit.

[0008] In one embodiment, the first data latching section and the second data latching section each includes a pair of cross coupled inverters.

[0009] In one embodiment, each one of the inverters in the pair is coupled across the pair of outputs of the data latching section therein.

[0010] In one embodiment, the first switch section comprises a CMOS transmission gate and the wherein the second switch section comprises a CMOS transmission gate/

[0011] With such an arrangement, the flip flop circuit according to the disclosure includes back to back inverters as holding latches, cross coupled or jam data latch across the true and complement (false) data channels thereby providing a static flip flop circuit with equal time delays to both the true and false data. The cross coupled inverter data latch is known for its ability to re-center voltage switch point near half supply voltage. This feature enables the flip flop to achieve greater speed when used in differential configuration since output true and false data arrive at the output at the same time. The latch is design into a gated latch through the use of transmission gates. The flip flop has a single transmission gate to inverter delay making the flip flop at a minimum of 2 times faster than existing design. The flip flop is also full differential and symmetrical which provides very high noise immunity to supply and ground bounces. As mentioned, the flip flop is fully differential improving noise immunity. The latency from output true and output false data are matched which lends itself more to differential applications, such as use in a dual pass gate logic family. The voltage switch point is restored through the data latches and proper sizing further increasing the speed of the flip-flop circuit. The flip flop uses the same number of clocked transistors as a traditional flip flop making it comparable in power to existing flip flops architectures. Finally, being a static flip flop, it does not require charge refreshing _s [0012] The details of one or more embodiments of the disclosure are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the disclosure will be apparent from the description and drawings, and from the claims.

DESCRIPTION OF DRAWINGS

[0013] FIG. 1 is a schematic diagram of a flip-flop circuit according to the PRIOR ART; and

[0014] FIG. 2 is a schematic diagram of a flip-flop circuit according to the disclosure.

[0015] Reference symbols in the various drawings indicate like elements.

DETAILED DESCRIPTION

[0016] Referring now to FIG. 1, a CMOS D-type flip-flop circuit 10 is shown having: a pair of binary data input terminals 12T, 12C, a first one of the pair of input terminals for receiving a true binary data input signal (D) and a second one of the pair of input terminals for receiving a complement of the true binary data input signal D ; and a pair of clock input terminals CLOCK, CLOCK , a first one of the pair of clock input terminals, CLOCK, for receiving a true clock signal and a second one of the pair of clock terminals, CLOCK , for receiving a complement of the true clock signals. It is noted that here, in this example, the clock pulse signals are implemented with positive edge clock pulses; it being understood that the circuit may be implemented with negative edge clock pulses by inverting CLOCK and CLOCK ; The flip flop circuit 10 is constructed in a master/slave data latch. One latch is transparent when the clock is active while the second (slave) latch is holding data or nontransparent. The master slave construction is what allows the flip flop circuit 10 to respond to a clock pulse edge.

[0017] More particularly, the flip-flop circuit 10 includes: a first logic signal storage circuit 1 1 A having a first input terminal 12T fed by the true logic signal D at terminal 12T and a second input terminal 12C fed by the complement of the true logic signal D at T US2014/040675 terminal 12C and a pair of output terminals 13 A, 13B; and, a second logic signal storage circuit 1 IB having a pair of input terminals coupled to the pair of output terminals 13 A,

13B the of the first logic signal storage circuit, 11 A and a pair of outputs D _0i Do .

[0018] In response to a first one of the clock signals (here when CLOCK goes low and CLOCK goes high): the first logic signal storage circuit 1 1 A passes the true and complement logic signals D, D fed thereto for storage circuit in the first logic signal storage circuit 1 1 A while the second logic signal storage circuit 1 IB prevents any the true and complement logic signals D, D previously stored in the first logic signal storage circuit 1 1A from passing from the pair of outputs 13 A, 13B to the second storage circuit 1 IB. In response to a subsequent one of the clock signals (here when CLOCK goes low and CLOCK goes high): the first storage circuit 1 1 A prevents the true and complement logic signals D, D fed thereto from passing for storage in the first storage circuit 11 A while the second storage circuit 1 IB passes the true and complement logic signals D, D stored in the first storage circuit 1 1A at the pair of outputs 13 A, 13B to the second storage circuit 1 IB for storage in the second storage circuit 1 IB. The stored true and

complementary signals D, D now stored in the second storage circuit 1 IB appear at the output terminals of the second storage circuit 1 IB as D ₀ , and D o, respectively.

[0019] The elements described above of the flip flop circuit 10 are formed on a common semiconductor integrated circuit chip and are implemented in CMOS technology. The time delay between a time the true logic signal D passes from the first input terminal 12T to a first one of the pair of outputs D ₀ of the second logic signal storage circuit is equal to the time delay between the time the complement of the true logic signal D at terminal 12C passes from the second input 12C to a second one of the pair of outputs D o of the second logic signal storage circuit 1 IB. The true logic signal D and the complement of the true logic signal D arrive at the outputs arrive at the outputs D ₀ and D ₀ at the same time. Thus, the true logic signal D and the complement of the true logic signal D arrive at the outputs arrive at the outputs D ₀ and D ₀ at the same time.

[0020] More particularly, the first logic signal storage circuit 1 1 A includes: (A) a first switch section 14A fed by: the true logic signal D at the first input terminal 12T (after passing through buffer inverter 16a) and the complement of the true signal D at the second input terminal 12C (after passing through buffer inverter 16b); and the clock pulses; and (B) a first data latching section 18A connected across outputs 18Aj, 1 8A ₂ of the first switch section 14A for storing the true logic signal D at a first one of the pair of outputs (terminal 13 A) of the first data latching section 18A and for storing the complement logic signal D at a second one of the pair of outputs (terminal 13B) of the first data latching section 18 A,

[0021] The second logic signal storage circuit 1 IB includes (A) a second switch section 14B fed by the clock signals and coupled to the pair of outputs 13A, 13B of the first data logic section 1 1 A (after passing through buffer inverters 15a, 15b in section 18A, as shown); and (B) a second data latching section 18B connected across outputs of the second switch section 14B for storing the true logic signal D at a first one of a pair of outputs 20Bi, 20B ₂ of the second data latching section and for storing the complement logic signal D at a second one of the pair of outputs of the second data latching section 18B.

[0022] More particularly, each one of the switching sections 14A, 14B includes a switch 14Ai. 14A ₂ , 14B] and 14B ₂ , each one being identical in construction, here each one is a CMOS transmission gate. More particularly, more particularly, the nMOS transistor of switch section 14Ai is fed by CLOCK , and the pMOS transistor of switch 14Aj is fed by CLOCK. The nMOS transistor of switch section 14A ₂ is fed by CLOCK , and the pMOS transistor of switch 14Ai is fed by CLOCK. The nMOS transistor of switch section 14Bi is fed by CLOCK, and the pMOS transistor of switch 14Bi is fed by CLOCK . The nMOS transistor of switch section 14B ₂ is fed by CLOCK, and the pMOS transistor of switch 14Ai is fed by CLOCK . Thus, the nMOS transistors of switches 14Ai and 14A ₂ are fed by

CLOCK , and the pMOS transistors of switches 14A] and 14A ₂ are fed by CLOCK, as shown. Therefore, in response to the positive edge of one clock pules, switch section 14A is closed to thereby transmit data fed to it to become stored in the first data latching section 18A and switch section 14B is open so that the data stored in first data latching section 18A does not pass for storage in the second data latching section 18B. Likewise, in response to the positive edge of the next clock pules, switch section 14A is open to thereby prevent data fed to it to become stored in the first data latching section 18A and switch section 14B is closed so that the data started in first data latching section 18 A does pass for storage in the second data latching section 18B.

[0023] The first data latching section 18A and the second data latching section 18B each includes a pair of cross coupled inverters 22a, 22b and 26a, 26b, respectively as shown. Each one of the inverters 22a, 22b and 26a, 26b in the pair is coupled across the pair of outputs of the data latching section therein, as shown. Thus, the input of inverter 22a is connected to terminal 18Aj and the output is connected to terminal 18A ₂ . Likewise, the input of inverter 22b is connected to terminal 18A ₂ and the output is connected to terminal 18Ai. In like manner, the input of inverter 26a is connected to terminal 20B[ and the output is connected to terminal 20B ₂ . Likewise, the input of inverter 26b is connected to terminal 29B ₂ and the output is connected to terminal 20Bi,

[0024] More particularly, the first data latching section 18A has a pair of terminal 18A], 18A ₂ , a first one of the pair of terminals 18Ai being coupled to an output of the first transmission gate 14Ai and a second one of the pair of output terminals 18A ₂ being coupled to an output of the second transmission gate 14A ₂ . A first inverter 22a has an input connected the output of the first transmission gate 14Ai and an output connected to the connected the output of the second transmission gate 14A ₂ ; and a second inverter 22b has an input connected the output of the second transmission gate 14A ₂ and an output connected to the connected the output of the first transmission gate 14A], as shown.

[0025] In like manner, the second data latching section 18B has a pair of terminal 20Ai, 20B ₂ , a first one of the pair of terminals 20Ai being coupled to an output of the first transmission gate 14Bj and a second one of the pair of output terminals 20A ₂ being coupled to an output of the second transmission gate 14B ₂ . A first inverter 26a has an input connected the output of the first transmission gate 14Bj and an output connected to the connected the output of the second transmission gate 14B ₂ ; and a second inverter 26b has an input connected the output of the second transmission gate 14B ₂ and an output connected to the connected the output of the first transmission gate 14B], as shown.

[0026] The flip-flop circuit 10 includes: a second pair of inverters 30a, 30b; a first one of the inverters 30a in the second pair of inverters being coupled to the first one of the pair of terminals 20Bi of the second data latching section 18B and a second one of the inverters 2014/040675

30b in the second pair of inverters being coupled to the second one of the pair of terminals 20B ₂ of the second data latching section 18B. The outputs of the inverters 30a, 30b are coupled to data output terminals D ₀ and D 0, respectively, as shown.

[0027] It should now be appreciated a flip-flop circuit fed by a true logic signal and the complement of the true logic signal according to the disclosure includes: a first logic signal storage circuit having a first input terminal being fed by the true logic signal and a second input terminal fed by the complement of the true logic signal, the first logic signal storage circuit having a pair of output terminals; a second logic signal storage circuit having a pair of input terminals coupled to the pair of output terminals of the first logic signal storage circuit; wherein, in response to one of the clock signals: the first logic signal storage circuit passes the true and complement logic signals fed thereto for storage in the first logic signal storage circuit while the second logic signal storage circuit prevents the true and complement logic signals stored in the first logic signal storage circuit from passing from the pair of outputs of the first logic signal storage to the second storage circuit; and in response to a subsequent one of the clock signals; the first logic storage circuit prevents the true and complement logic signals fed thereto from passing for storage in the first storage circuit while the second storage circuit passes the true and complement logic signals stored in the first storage circuit at the pair of outputs of the first storage circuit to the second storage circuit for storage in the second storage circuit. The flip-flop circuit may include one or more of the following features either independently or in combination with another feature including: wherein the true and complement logic signals stored in the first logic signal storage circuit are produced at the pair of outputs of the first logic signal storage circuit and the true and complement logic signals stored in the second logic signal storage circuit are produced at a pair of outputs of the second logic signal storage circuit; wherein the time delay between a time the true logic signal passes from the first input terminal to a first one of the pair of outputs of the second logic signal storage circuit is equal to the time delay between the time the complement of the true logic signal passes from the second input to a second one of the pair of outputs of the second logic signal storage circuit; wherein the first logic signal storage circuit comprises: a first switch section fed by: the true logic signal at the first input and the complement of the true signal at the second input; and the clock pulses, and a first data latching section connected across outputs of the first switch section for storing the true logic signal at a first one of T U 2014/040675 the pair of outputs of the first data latching section and for storing the complement logic signal at a second one of the pair of outputs of the first data latching section, the second logic signal storage circuit comprises a second switch section fed by the clock signals and coupled to the pair of outputs of the first data logic section, a second data latching section connected across outputs of the second switch section for storing the true logic signal at a first one of a pair of outputs of the second data latching section and for storing the complement logic signal at a second one of the pair of outputs of the second data latching section, wherein, in response to a first one of the clock signals, the first switch section pass the true and complement logic signals fed thereto to the first data latching section while the second switch section prevents the true and complement logic signals from passing from the pair of outputs of the first data latching section to the second latch section; and in response to a second, subsequent one of the clock signals, the first switch section prevents the true and complement logic signals fed thereto from passing to the first data latching section while the second switch section pass the true and complement logic signals from the pair of outputs of the first data latching section to the second latch section; wherein the first data latching section and the second data latching section each includes a pair of cross coupled inverters; wherein each one of the inverters in the pair is coupled across the pair of outputs of the data latching section therein; or wherein the first switch section comprises a CMOS transmission gate and the wherein the second switch section comprises a CMOS transmission gate.

[0028] It should now also be appreciated a flip-flop circuit according to the disclosure includes: a pair of binary data input terminals, a first one of the pair of input terminals for receiving a true binary data input signal and a second one of the pair of input terminals for receiving a complement of the true binary data input signal; a pair of clock input terminals, a first one of the pair of clock input terminals for receiving a true clock pulse and a second one of the pair of clock terminals for receiving a complement of the true clock pulse; a first switch section to the pair of clock input terminals, comprising: a first switch connected to the first one of the pair of input terminals; and a second switch connected to the second one of the pair of input terminals; a first data latching section having a pair of terminal, a first one of the pair of terminals of the first data latching section being coupled to an output of the first switch and a second one of the pair of output terminal of the first data latching section being coupled to an output of the switch; a first 2014/040675 pair of inverters; a first one of the inverters in the first pair of inverters being coupled to the first one of the pair of terminals of the first data latching section and a second one of the inverters in the first pair of inverters being coupled to the second one of the pair of terminals of the first data latching section; a second switch section connected to the pair of clock input terminals comprising: a first switch, connected to an output of the first one of the pair of inverters; and a second switch, connected to an output of the second one of the pair of inverters; a second data latching section having a pair of, a first one of the pair of terminals of the second data latching section being coupled to an output of the first switch of the first transmission gate section and a second one of the pair of output terminal of the second data latching section being coupled to an output of the second switch of the first transmission gate section; and a second pair of inverters; a first one of the inverts in the second pair of inverters being coupled to the first one of the pair of terminals of the second data latching section and a second one of the inverters in the second pair of inverters being coupled to the second one of the pair of terminals of the second data latching section. The flip-flop circuit may include one or more of the following features either independently or in combination with another feature including: wherein the first data latching section includes: a first inverter having an input connected the output of the first transmission gate of the first transmission gate section and an output connected to the connected the output of the second transmission gate of the first transmission gate section, and a second inverter having an input connected the output of the second transmission gate of the first transmission gate section and an output connected to the connected the output of the first transmission gate of the first transmission gate section; wherein the second data latching section includes: a first inverter having an input connected the output of the first transmission gate of the second transmission gate section and an output connected to the connected the output of the second transmission gate of the second transmission gate section, and a second inverter having an input connected the output of the second transmission gate of the second transmission gate section and an output connected to the connected the output of the first transmission gate of the second transmission gate section.

[0029] A number of embodiments of the disclosure have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the disclosure. For example, while a D type flip flop has been shown, the circuit may be suitably modified to form a J-K flip flop or a flip flop with 14 040675 asynchronous or synchronous reset or preset, for example. Further, the flip flop may be implemented in DVL (Dual Value Logic) or DPL (Double Pass-Transistor Logic). Accordingly, other embodiments are within the scope of the following claims.