FULLY INTEGRATED OSCILLATOR FOR ULTRA LOW VOLTAGE APPLICATIONS WHICH QUADRUPLES VOLTAGE AND HAS LOW PHASE NOISE

Technical Field

The present invention is related to a self starting oscillator which increases DC (Direct Current) voltage with a coefficient factor of 4 or more, by using a primary and a secondary LC tank in order to provide a differential sinusoidal output voltage which corresponds to high amplitude, low phase noise and high purity. The circuit design described in the present invention is suitable for ultra low voltage applications together with particularly low cost and high integration.

Prior Art

Oscillators are key components used to establish periodic signals as in for example clocks used in synchronous digital systems, in carrier signals for communication and in charge pump stimulators in DC-DC converters. LC tank oscillators have been used in various applications due to their outstanding performance in terms of minimum operation voltage, self operation ability, low phase noise and high output voltage amplitude. However the performance of the LC tank is dependent actually on the inductor quality factor and the ability to compensate real losses in a single cycle. Inductors integrated to the chip typically have high resistance and low quality factor. These inductive real losses are compensated with negative resistance created from active devices such as cross connected NMOS pairs. The active devices contribute to the increase in phase noise shown in the Leeson equation 1 together with the extra resistance added to the system and the lowered oscillation amplitude. Therefore, high profit, integrated low cost oscillators relating to low voltage and low power applications are key obligations for the integrated device market.

In the recent years several circuit inventions have been provided which address the problems related to integrated LC tank voltage controlled oscillator (VCO) topologies relating to low power applications with low voltage levels. The transformer return VCO, has been provided with the reference number [1] in order to increase performance in terms of oscillation purity and voltage amplitude. However the applied tank capacitor has led to

1

SUBSTITUTE SHEETS (RULE 26) distortions in oscillation amplitude and the inductive coupling mechanism has limited minimum operation voltage. In the reference with the number [2] the application of the medium level cross transformer coupling provides good phase noise and power consumption, however it reduces voltage gain. The references numbered [3], [4] and [5] published in the recent years provide low power VCO design together with a 1 V input. However the applied additional active devices (MOSFET's - Metal Oxide Semi Conductor Field Effect Transistors) increase phase noise and reduce oscillation purity. The double resonance LC tank set forth by the reference number [6] has double band switching ability with the mutual LC tank having a 0,8 V input, however the phase noise is significantly high even in the double digit frequency range. The reference numbered [7] provides the method of re-using the current in order to improve the power consumption of the VCO. However the voltage gain in such an order due to the amplitude imbalances of differential outputs is limited with the unit. The asymmetrical structure of the VCO increases phase noise up to -98 dBc/Hz at 1 Mhz frequency and 5,96 GHz. The harmonic tuned LC tank provided by the reference number [8], has low phase noise at 2 GHz, but offers less than 2x amplitude gain and poor oscillation purity . The NMOS differential oscillator which has two inductors presented with the reference number [9] has low phase noise and low jitter due to the symmetry of the oscillator, however the amplitude gain is less than two folds. The low voltage VCO topology provided by the reference number [10] has weak performance during an ultra low voltage operation due to the number of the active components such as diodes, resistances and transistors. The voltage adjustable LC tank set forth with the reference number [11] has better phase noise than -137 dBc/Hz for the 400 to 1300 MHz frequency band, and has an offset of 100 kHz at 5 V input. As the current at the 5 V input is limited with 15mA, this design suffers from low current drive. The PMOS cross connected LC tank set forth by the reference number [12] is suitable for low power applications due to its low power consumption and low phase noise, however the oscillator has insufficient charge drive and unity gain. Therefore, the design does not provide a solution relating to ultra low voltage applications together with the input voltage under threshold voltage of the CMOS (Complementary Metal-Oxide-Semiconductor) technology. The most frequently proposed LC tank VCO's suffer from oscillation purity and output voltage oscillation, and degraded phase noise due to the number of active components in the VCO and the input voltage limitation.

The application of a secondary LC tank as a booster element for the primary LC tank has been suggested in the reference numbered [13] in order to reduce phase noise. However the six MOSFET's used has increased phase noise and it has limited this noise to > -150 dBc/Hz at a 1MHz offset. The cross connected PMOS pair as referred to in number [13] reduces oscillation while it limits the load current and minimum operation voltage. Additionally the cost is inherently higher in the reference numbered [13] in comparison to the present invention due to higher number of components.

Forward body bias technique has been disclosed in the reference numbers [14], [15] and [16] together with capacitive feedback, current reuse with bottom series coupling, and core current control respectively, to improve the LC tank performance in terms of amplitude gain, phase noise and low power consumption at low voltage operation. Despite the filtering techniques presented in the reference number [17] in order to increase phase noise performance, additional MOSFET's contribute to power loss and reduce voltage gain. Most of the circuits described above oscillate with a minimum frequency range of several Ghz. On the other hand a fully integrated, low cost, self-starting oscillator design with low supply voltage range is required for MFIz frequency applications, such as short wave data communication, DC-DC converter design, etc. In addition, body biasing techniques increase the design and fabrication cost significantly for conventional CMOS processes.

The problems that have been defined above are eliminated by means of the invention.

Aims of the I nvention and Brief Description

The invention is related to a fully integrated, oscillator for ultra low voltage applications which quadruples voltage and has low phase noise.

The fully integrated, oscillator for ultra low voltage applications which quadruples voltage and has low phase noise according to the present invention aims to provide the following;

• increasing the output voltage amplitude via the secondary LC tank,

• increasing the output power capacity via the secondary LC tank,

• reducing phase noise via the secondary LC tank,

• self-starting oscillator signals with different amplitude, duty cycle and frequency,

• contributing to the correct switching mechanism of the oscillator in order to improve oscillation purity and phase noise, • comprising the secondary LC tank output used as the NMOS switching gate voltage in order to control the operation of the oscillator,

• comprising high voltage switching controls,

• providing completely switched off N-channel MOSFET's via the negative peak point of the secondary LC tank,

• decreasing the leakage to improve the oscillation performance and power dissipation by the negative peak of the secondary LC tank,

• using the secondary LC tank output as the oscillator output,

• being formed of the oscillator that has low phase noise and good oscillation purity.

According to an aspect of the present invention the invention comprises a primary LC tank that is serially connected to the secondary LC tank at the peak amplitude of the LC tank output node which quadruples voltage.

According to another aspect the invention comprises a cross connected N-channel MOSFET (NMOS) pair as a negative resistance generator.

According to another aspect the invention comprises a cross connected switching pair characterized by a control pair in relation to two LC oscillators (primary and secondary) that operate synchronously.

According to another aspect the present invention comprises a secondary LC tank which quadruples (4x) output amplitude voltage in comparison to the input voltage amplitude, increases output power capacity and reduces phase noise; the said secondary LC tank's output is used as NMOS switch gate voltage to control the oscillator operation and the oscillator's output is generated by the secondary LC tank's output and the secondary LC tank cooperates with a primary LC tank, the secondary LC tank of voltage quadrupling LC tank is formed between the gate of the one NMOS and the drain of the other NMOS, the secondary LC tank's output has full sine wave oscillations, while the primary LC tank has half wave oscillations due to the ground connected NMOS, the secondary LC tank is form of the parallel combination of the C2 capacitor with L2 inductor.

Another aspect of the present invention comprises a high voltage switching control characterized by completely turning off the NMOS by using the negative peak point of the secondary LC tank and reducing leakage in order to reduce power losses and improve oscillation performance.

Another aspect of the invention comprises an LC tank pair characterized by having at least two active components which are two N-channel MOSFET's.

Another aspect of the invention comprises a secondary LC tank pair characterized by having at least 4 passive components which are two inductors and two capacitors.

Another aspect of the invention comprises a primary LC tank pair characterized by having at least 2 passive components which are two inductors.

Another aspect of the present invention comprises an LC tank characterized by having an LC tank output connected to the active NMOS device gate terminal which quadruples voltage.

Another aspect of the present invention comprises an LC tank characterized by having an LC tank which quadruples voltage having the ability to form a pair of differential (180° phase deviation) signals having < 1 GHz oscillation.

Another aspect of the present invention includes LC tank characterized by The primary and the secondary oscillators of the voltage quadrupling LC tank that are in series once the corresponding MOSFET is switched off.

Another aspect of the present invention comprises an LC tank characterized by having a only one power supply from the system input.

Another aspect of the invention comprises two optional Ci capacitors as a part of the primary LC tank pair which can be replaced with the parasitic capacitance of inductors and switches in integrated designs as a Co.

Another aspect of the invention comprises an optional Co bypass capacitor located between the right side and left side LC tanks in the LC tank pair . Another aspect of the invention comprises N-channel MOSFETs characterized by having two N-channel MOSFET (NMOS) in the oscillator.

Yet another aspect of the invention comprises an LC tank characterized by the implemetation of the LC tank in the 180 nm CMOS technology which can operate automatically with a low input voltage as low as 0,09 V in order to sustain oscillations with an amplitude of 0,36 V.

Definition of the Figures of the I nvention

The figures have been used in order to further disclose the oscillator developed by the present invention which has low phase noise and which quadruples voltage and which is fully integrated for ultra low voltage applications and the figures have been described below:

Figure 1: LC tank based oscillator which quadruples the voltage.

Figure 2: Half circuit analysis of the primary oscillator.

Figure 3: Half circuit analysis of the secondary oscillator.

Figure 4: Characteristic curves relating to the LC tank which quadruples the voltage.

Detailed Description of the I nvention

Fully Integrated voltage quadrupling and low phase noise oscillator for ultra low voltage applications developed with this invention consists of a novel oscillator circuit design which produces a sinusoidal signal output with at least quadrupled peak-to-peak amplitude compared to the input DC voltage supply.

Various terms to better describe the fully integrated oscillator for ultra low voltage applications which quadruples voltage and has low phase noise have been presented and disclosed below.

Terminology:

C: Capacitor

L: Inductor Co: Optional bypass capacitor

Ci: Primary capacitor

C2: Secondary capacitor

Li: Primary inductor

L : Secondary inductor

NMOS: N-channel MOSFETs

VDD: Positive supply voltage (input source)

CLK1: oscillator output node 1

CLK2: oscillator output node 2

Nl: The first of the N-channel MOSFET pair

N2: The second of the N-channel MOSFET pair

CL: Load capacitor (C-load)

RL: Load resistance parallel with the load capacitor (R-load)

LC: (Inductor - Capacitor) formed of an inductor and capacitor

The present invention has been described in detail below.

The fully integrated oscillator developed by the present invention for ultra low voltage applications which quadruples voltage and has low phase noise is formed of an oscillator. The oscillator, comprises an LC tank comprising a primary LC tank and a secondary LC tank, a cross connected switch pair which can be implemented with a pair of N-channel MOSFET's (NMOS), and self-generated signals having different duty cycles and a high voltage switch control.

The oscillator has desirable characteristic features such as low phase noise and frequency stability in addition to high output voltage amplitude. Therefore the aim of the invention is reached by means of the two LC oscillators (primary and secondary) which operate in synchronization with each other and which are controlled by a pair of cross connected switch pairs. As shown in Figure 1, the control switches can be used with N- channel MOSFET's (NMOS). The input in the Figure (VDD), is the input supply voltage. (CLK1) and (CLK2) represent two output sinusoidal signals having 180° phase offset relative to each other. The negative resistance of the cross connected differential NMOS pair, compensate the real losses received from passive components. Co is an optional bypass capacitor to modify the amplitude and frequency characteristics of the primary oscillator. The capacitor (Ci) of the primary oscillator can be replaced with the parasitic capacitance of inductors and switches in integrated designs and it does not have to be an explicit capacitor. The parallel combination of C2 with L2 forms the secondary LC tank.

A detailed description of an invention is presented with model based circuit analysis. The basic working mechanism of the primary LC tank is analyzed through Figure 2. A capacitor stores energy in the form of electrical charge, which generates a voltage across it. An inductor stores energy in its magnetic field, depending on the current through it. The inductor peak current with fully discharged Ci capacitor leads to convey input voltage (VDD) to node A in Figure 2. If N2 is off and Ci is fully charged as shown in Figure 2(a), then current will start to flow through the inductor, reducing the A voltage and building up a magnetic flux on Li. Eventually Ci is discharged, and voltage across it reaches zero. But the current will continue to flow as shown in Figure 2(b), because the current through an inductor cannot change instantaneously. Now the voltage at node A is VDD. The current starts to charge the capacitor in opposite polarity to its initial state. If N2 is ON just after the start of capacitor charging, the capacitor will directly connect to the ground and charge to VDD instantly. Once the magnetic field is completely dissipated, the current through the inductor will be zero as illustrated in Figure 2(c). The current will start to flow in the opposite direction through the inductor due to the voltage across it (presence of the charged capacitor in parallel). Since N2 is still ON, the current will be sourced by the input power source. This inductor current is stored as energy in form of magnetic field at Li. Once N2 is off, Ci starts to discharge through the Li. When current through Li reaches its peak, Ci is fully discharged as shown in Figure 2(d). Therefore, the inductor will store energy from Ci capacitor and energy from input source (VDD) simultaneously. At this instant, voltage at node A is VDD. The zero voltage across the Ci capacitor causes the current through Li to stop, but Li resists change in its current, so the reduction of current is gradual. Therefore, current will continue in the same direction, but will decrease as the Li magnetic flux discharges through the Ci capacitor. This inductor current will charge the Ci capacitor to ~2VDD, which will result in ~3VDD at node A as illustrated in Figure 2(e). Then the cycle will begin again, with the reverse current through the inductor.

The secondary LC tank half circuit model analysis is shown in Figure 3. Since CLK1 (oscillator output node) and node A has different zero-crossing as illustrated in Figure 4(a), the peak current through the L inductor does not coincide with the Li peak current, as depicted in Figure 4(b). The current from N2 drain to primary LC tank inductor is assumed negative in the figure, while current from N2 drain to C2 and L2 is positive. The L2 peak current is synchronized with the C2 peak current, but is opposite in direction as illustrated in Figure 4(b). The zero voltage across the capacitor C2 due to fully discharged state causes it to start charging. At this instant voltage levels at nodes A and CLK1 are equal (ground). The simultaneous zero current through L2 and C2 results in minimum voltage at the output. Once, N2 is off and CL, C2 are fully charged as shown in Figure 3(a), voltage at node A < CLK1. Then C2 and CL will discharge through L2 and f¾_, while accumulating magnetic energy in l_2. Since C2 is discharging, this current will not flow into the primary LC tank. The fully discharged C2 and CL conduct the maximum L2 current by delivering zero voltage at node A and CLK1 as in Figure 3(b). Then L2 starts to contribute to the current in the same direction, and starts to charge the capacitors. Since N2 is switched on, some portion of the current flows through NMOS, and sinks to the ground. Finally, capacitors charge as shown in Figure 3(c), and create the minimum voltage at CLK1 (<-2V _D D). Then C2 starts to discharge through L ₂ inductor while CL is charging as shown in Figure 3(d). Simultaneously, since the primary LC tank capacitor is fully charged, Li inductor current is flowing through L2 due to the negative voltage at CLK1 with respect to the ground connection at NMOS drain. The fully discharged C _L and C stop the current loop while the grounded voltage at node A is conveyed to CLK1. Since the inductor resists change in current, L ₂ starts to discharge the magnetic energy by producing current in the same direction. This current will start to charge the capacitors, but the current through C2 capacitor will sink to ground due to N2 ON condition (A = 0V) as shown in Figure 3(d). Once voltage increases at CLK1, the majority of current starts to flow through the load and C2 current will reduce with switched off N2 as shown in Figure 3(e). Therefore, CL current will be maximum and will increase CLK1 voltage. The increase in CLK1 voltage with respect to node A decreases the CL current and allows increase of C2 current in the same direction again. Once CL is fully charged (CL current is zero), the voltage at CLK1 is at maximum as shown in Figure 3(f) with secondary peak current through the C2 as illustrated in Figure 4(b). Then CL and C2 start to discharge through L inductor while reducing the voltage at CLK1. This loop will continue until disconnection at the external power source (VDD). The voltage across C2 capacitor varies from -2V _D D to 2V _D D with respect to node A as shown in Figure 4(c). When CLK1 voltage peaks, C2 voltage is < 2VDD and > VDD according to C2 capacitance. Higher C2 capacitance will produce higher CLK1 voltage due to lower C2 impedance and higher time constant. On the other hand, increase in CL causes reduction in the peak CLK1 voltage, resulting in reduction in the current passing through C2.

Low phase noise is one of the main criteria for an oscillator design in several low power applications such as wireless and wired communication, charge pump clock signals, data converters and sensors. The low noise oscillator is an advantage for any kind of clocked system in terms of performance. A general definition relating to the phase noise of an oscillator is provided with the Leeson formula according to equation (1):

wherein (T) is heat by Kelvin, (wo) is oscillation frequency, (Q) is tank quality factor, (Dw) is the offset from the carrier, (Psig) is the signal power, (F) is a constant (noise factor) and (k) is the Boltzmann constant. In the present invention the described oscillator, has low phase noise even under low load resistance due to the high output amplitude which causes high signal power. For example an embodiment of the circuit described, provides -180 dBc/FIz phase noise at a frequency offset of 1-MFIz in relation to the 2 kQ (RL) and 10 pF (CL) parallel RC load at the 0,2 V DC input.

The present invention provides a VCO implementation which is suitable for low voltage and low power operation. The performance of the oscillator has been significantly improved in terms of input voltage, voltage amplitude gain, low phase noise, oscillation purity and high output power capacity by the addition of a secondary LC tank to the primary LC tank. Therefore, the implemented design improves the performance of applications such as low noise energy transfer, quality frequency synthesis, improved phase lock loop and low voltage energy harvesting. An implementation of the LC tank in 180nm CMOS technology can self start with input voltage as low as 0.09 V to successfully sustain the oscillations with an amplitude of 0.36 V. The LC tank which quadruples the applied voltage, is suitable for generating sinusoidal signals from input voltages even lower than the MOSFET threshold voltage in a given technology.

The present invention shall be understood more clearly form the features described below.

The present invention comprises a cross connected MOSFET (NMOS) pair as a negative resistance generator. The LC tank oscillator which quadruples the voltage has high output voltage and low input operation voltage, and as a result it allows operation at very low voltages in the present invention. Additionally the output node (secondary LC tank output) has full sinusoidal wave oscillation, whereas the primary LC tank, has a half wave oscillation due to the ground connected NMOS. Another important feature of the present invention is the fully integrated LC tank which quadruples the voltage and has an oscillation ability at < 1 GHz oscillation frequency. The primary and the secondary oscillators of the LC tank which quadruple voltage are in series once the corresponding MOSFET is switched off. By this means the LC tank based oscillator which quadruples the voltage has higher oscillation amplitude for a given ultra low input voltage. Moreover the LC tank oscillator which quadruples the voltage, has a minimum number of circuit components (active and passive) in order to meet the fully integrated primary and secondary oscillator requirements in the present invention in relation to low cost and low profile systems. The minimization of active components reduces the phase noise of the oscillator which quadruples voltage in very low voltage applications. The secondary LC tank of voltage quadrupling oscillator is formed between the gate of one NMOS and the drain of the other NMOS, The differential outputs of the voltage quadrupling LC tank is connected to the gate terminals of the active NMOS devices. The circuit does not need any external voltage other than the input voltage. It means that The secondary LC tank of voltage quadrupling oscillator does not need a separate power source. The primary LC tank is in series with the secondary LC tank at the peak amplitude of the output node of voltage quadrupling LC tank. In this way, voltage quadrupling LC tank has a higher voltage gain.

A fully integrated oscillator for ultra low voltage applications which quadruples voltage and has low phase comprises:

• A self-starting oscillator circuit that has a primary LC tank pair, a secondary LC tank pair and a switch pair in order to provide negative resistance for forming a differential sinusoidal AC pair, in other words frequency having a 180° phase offset and to form a fixed amplitude of two output signals.

• A primary LC tank circuit that consists of one inductor and one capacitor in parallel to the inductor. One of the primary LC tank pair is connected between the first switch and input supply, and the second of the primary LC tank pair is connected between the second switch and input supply. In such an embodiment, there are thus two inductors and two capacitors in the primary LC tank circuit.

• According to another embodiment of the primary LC tank circuit, a capacitor is provided which is connected to the switch part of the LC tank and which is known as the bypass capacitor. The bypass capacitor can be used to change the output signal frequency and amplitude. • According to an embodiment which has been specifically designed for integrated, low cost systems, the primary LC tank capacitors are provided via the parasitic (intrinsic) capacitances of peripheral circuits such as the capacitance of the node which connects to the secondary oscillator. In such an embodiment, a certain primary capacitor is not required.

• Two active circuit components serving as a switch pair to provide negative resistance in order to maintain constant oscillation amplitude and frequency. Each switch in the pair is connected to one of the primary LC tank circuits.

• In one embodiment, each switch can be implemented with one N-channel MOSFET. In other embodiments, other controlled switching devices can be used.

• A secondary LC tank formed of an inductor and a capacitor parallel to the inductor. A part of the secondary LC tank, is connected between the primary MOSFET drain and the secondary MOSFET gate. Another part of the secondary LC tank, is connected between the secondary MOSFET drain and the primary MOSFET gate. According to such an embodiment two inductors and two capacitors are provided in the secondary LC tank circuit.

• Signals having different duty cycles which are automatically created are used in the gate and drain terminals of MOSFET's and they enable to close and open the NMOS switches completely and they contribute to the suitable switching mechanism of the oscillator in order to improve oscillation purity and reduce phase noise.

References

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Table 1: Performance comparison tables of some VCO's implemented in the recent years in relation to low voltage applications.