Title:
FULLY VALID-GATED READ AND WRITE FOR LOW POWER ARRAY
Document Type and Number:
WIPO Patent Application WO/2016/175958
Kind Code:
A3
Abstract:
In an array (200) that qualifies each row according to a valid/invalid state, each row may each include valid-gated read circuitry (220) to conditionally block a read wordline according to the state of a valid bit cell (224) from toggling unless the row stores a data word that has a valid state or a read force signal is asserted. Furthermore, in a write operation, each row may have valid-gated write circuitry (320) that conditionally blocks a write wordline from toggling unless input data to be written to the row has a valid state or a write force signal is asserted. Moreover, output latch clocking may be blocked from toggling unless a row to be read stores a data word that has a valid state or the read force signal is asserted, and input latch clocking may also be blocked unless the input data to be written has a valid state or the write force signal is asserted.
Inventors:
HOFF DAVID PAUL (US)
MARTZLOFF JASON PHILIP (US)
SWEITZER ROBERT ANDREW (US)
MARTZLOFF JASON PHILIP (US)
SWEITZER ROBERT ANDREW (US)
Application Number:
PCT/US2016/024478
Publication Date:
December 15, 2016
Filing Date:
March 28, 2016
Export Citation:
Assignee:
QUALCOMM INC (US)
International Classes:
G11C7/12; G11C7/10; G11C8/08; G11C11/419
Foreign References:
| US20110141826A1 | 2011-06-16 | |||
| US20090244992A1 | 2009-10-01 | |||
| US20140340135A1 | 2014-11-20 | |||
| US20070171757A1 | 2007-07-26 |
Attorney, Agent or Firm:
CICCOZZI, John L. et al. (Geissler Olds & Lowe, P.C.,4000 Legato Road,Suite 31, Fairfax Virginia, US)
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