Title:
FUSE MEMORY CIRCUIT AND SEMICONDUCTOR DEVICE
Document Type and Number:
WIPO Patent Application WO/2023/276733
Kind Code:
A1
Abstract:
A first fuse unit 110 and a second fuse unit 120 have the same configuration. A rectifier element 112 is connected in parallel to the fuse element. The drain of a first transistor M11 is connected to a second terminal of the fuse element F11, the source thereof is connected to a second line 104, and the gate thereof is connected to a program terminal PROG1. The source of a second transistor M12 is connected to a second terminal of the fuse element F11, the drain thereof is connected to an output terminal OUT1, and the gate thereof is connected to a test terminal TEST1. The drain of the third transistor M13 is connected to the output terminal, and the source thereof is connected to the second line 104.
Inventors:
TSUJI MASANOBU (JP)
Application Number:
PCT/JP2022/024376
Publication Date:
January 05, 2023
Filing Date:
June 17, 2022
Export Citation:
Assignee:
ROHM CO LTD (JP)
International Classes:
G11C17/16; G11C29/04; G11C11/412
Foreign References:
| JPH07105685A | 1995-04-21 | |||
| JP2014522134A | 2014-08-28 |
Attorney, Agent or Firm:
MORISHITA Sakaki (JP)
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