Title:
GALVANIC ISOLATION TRANSFORMER
Document Type and Number:
WIPO Patent Application WO/2012/012108
Kind Code:
A3
Abstract:
An integrated circuit die system comprises a first integrated circuit die, a second integrated circuit die and a transformer formed on a dielectric (e.g., quartz) substrate and electrically connected between the first integrated circuit die and the second integrated circuit die to provide galvanic isolation therebetween.
Inventors:
FRENCH WILLIAM (US)
HOPPER PETER J (US)
SMEYS PETER (US)
GABRYS ANN (US)
ANDERSON DAVID I (US)
HOPPER PETER J (US)
SMEYS PETER (US)
GABRYS ANN (US)
ANDERSON DAVID I (US)
Application Number:
PCT/US2011/041951
Publication Date:
April 26, 2012
Filing Date:
June 27, 2011
Export Citation:
Assignee:
NAT SEMICONDUCTOR CORP (US)
FRENCH WILLIAM (US)
HOPPER PETER J (US)
SMEYS PETER (US)
GABRYS ANN (US)
ANDERSON DAVID I (US)
FRENCH WILLIAM (US)
HOPPER PETER J (US)
SMEYS PETER (US)
GABRYS ANN (US)
ANDERSON DAVID I (US)
International Classes:
H01F38/40; H01L25/00
Foreign References:
| US7064442B1 | 2006-06-20 | |||
| US20030042571A1 | 2003-03-06 | |||
| US20080013635A1 | 2008-01-17 | |||
| US6107674A | 2000-08-22 | |||
| US5747982A | 1998-05-05 |
Other References:
See also references of EP 2589055A4
Attorney, Agent or Firm:
POLLOCK, Michael, J. (Three Embarcadero Center Suite 41, San Francisco CA, US)
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