Title:
GATE BIAS CONTROL CIRCUIT AND GATE BIAS CONTROL METHOD FOR COMMUNICATION AMPLIFICATION TRANSISTOR
Document Type and Number:
WIPO Patent Application WO/2023/188245
Kind Code:
A1
Abstract:
A gate bias control circuit (100) comprises: a wave detection unit (10) for detecting an input signal that is of a communication amplification transistor FET, that is a modulation wave signal obtained by modulation of a carrier wave, and that is inputted to a gate electrode as an input signal; and a bias voltage generation unit (20) that applies a gate bias voltage Vgt, according to input electric power of the input signal having been detected by the wave detection unit (10), to a gate bias node to which the gate electrode of the communication amplification transistor is connected.
Inventors:
YAMAGUCHI YUTARO (JP)
Application Number:
PCT/JP2022/016459
Publication Date:
October 05, 2023
Filing Date:
March 31, 2022
Export Citation:
Assignee:
MITSUBISHI ELECTRIC CORP (JP)
International Classes:
H03F1/02; H03F3/21
Domestic Patent References:
| WO2021182067A1 | 2021-09-16 |
Foreign References:
| JP2003338713A | 2003-11-28 |
Attorney, Agent or Firm:
SANNO PATENT ATTORNEYS OFFICE (JP)
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