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Patent Searching and Data


Title:
GATE DRIVE CIRCUIT AND GATE DRIVE METHOD
Document Type and Number:
WIPO Patent Application WO/2019/207977
Kind Code:
A1
Abstract:
The purpose of the present invention relates to suppressing the fluctuation of gate-source voltage in a gate drive circuit using SiC voltage-driven semiconductor elements. In order to achieve this purpose, according to the present invention, the gate drive circuit is configured such that: a P-type MOSFET and an N-side MOSFET are connected in series and the N-side MOSFET is directly connected to a negative side power supply; and an output stage lying in between the P-type MOSFET and the N-side MOSFET is negatively biased while a SiC voltage-driven semiconductor element is OFF. According to the present invention, since the output stage is constituted by a MOSFET having a small transient impedance, it is possible to suppress the fluctuation of gate-source voltage when driving the SiC voltage-driven semiconductor element. Since the gate is negatively biased while the SiC voltage-driven semiconductor element is OFF, it is possible to prevent erroneous ON. Accordingly, it is possible to provide a highly reliable gate drive circuit suitable for driving a SiC element.

Inventors:
SUZUKI, Hiroshi (6-6, Marunouchi 1-chome, Chiyoda-k, Tokyo 80, 〒1008280, JP)
KURIHARA, Naoki (6-6, Marunouchi 1-chome, Chiyoda-k, Tokyo 80, 〒1008280, JP)
Application Number:
JP2019/009651
Publication Date:
October 31, 2019
Filing Date:
March 11, 2019
Export Citation:
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Assignee:
HITACHI, LTD. (6-6 Marunouchi 1-chome, Chiyoda-ku Tokyo, 80, 〒1008280, JP)
International Classes:
H02M1/08; H03K17/08; H03K17/0812
Attorney, Agent or Firm:
Patent Corporate Body Dai-ichi Kokusai Tokkyo Jimusho (5-12, Iwamotocho 3-chome Chiyoda-k, Tokyo 32, 〒1010032, JP)
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