GATE DRIVING CIRCUIT AND DISPLAY PANEL

WIPO Patent Application WO/2022/017041

A1

A gate driving circuit and a display panel. The gate driving circuit (100) comprises a plurality of cascaded shift register units (110). The plurality of cascaded shift register units (110) comprise: a first shift register unit (111), comprising a first clock signal end (111A); a (n+1)th shift register unit, comprising a (n+1)th clock signal end; a second shift register unit (112), comprising a second clock signal end (112A); and a (n+2)th shift register unit, comprising a (n+2)th clock signal end. The gate driving circuit (100) further comprises a first clock signal line (CLK1) that is connected to the first clock signal end (111A) and the (n+1)th clock signal end, and a second clock signal line (CLK2) that is connected to the second clock signal end (112A) and the (n+2)th clock signal end; the first clock signal line (CLK1) and the second clock signal line (CLK2) are arranged at an interval; the input end of the first clock signal line (CLK1) is connected to one end of a first resistor (R1); the input end of the second clock signal line (CLK2) is connected to one end of a second resistor (R2); and the second resistor (R2) is greater than the first resistor (R1). Therefore, the gate driving circuit can improve or even eliminate a horizontal fine line phenomenon.

LIU RONGCHENG (CN)
AI ZHENGWEI (CN)
GONG WENJUN (CN)

PCT/CN2021/099152

January 27, 2022

June 09, 2021

Click for automatic bibliography generation  

BOE TECHNOLOGY GROUP CO LTD (CN)
WUHAN BOE OPTOELECTRONICS TECH CO LTD (CN)

G09G3/36

CN102598144A	2012-07-18
CN111028759A	2020-04-17
CN108877639A	2018-11-23
CN109272921A	2019-01-25
CN103093826A	2013-05-08
US20160379586A1	2016-12-29

LIU, SHEN & ASSOCIATES (CN)

View/Download PDF      PDF Help

Previous Patent: SPEECH SYNTHESIS METHOD AND SYSTEM

Next Patent: DISPLAY DEVICE AND DRIVING METHOD THEREFOR