FIELD OF THE INVENTION

Embodiments of the invention are in the field of semiconductor devices and processing and, in particular, formation of radio frequency (RF) transistors with precision resistors for reducing coupling between the gate electrode and the source and drain electrodes, and methods of forming such devices.

BACKGROUND OF THE INVENTION RF switches are needed in RF front end circuitry to rout the RF signals between components, such as RF filters, antennas, RF power amplifiers, and RF low-noise amplifiers. In order to increase the data rate of RF systems, the switching frequency needs to be increased. Currently data sent at 5G speeds needs a switching frequency of approximately 3.5 GHz or higher. This switching frequency is expected to increase as more data is consumed and delivered over wireless networks. One currently available RF switch that may be used to provide high switching frequencies is a high-k dielectric GaN transistor.

BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1A is a plan view illustration of an RF switch with a serpentine shaped resistor, according to an embodiment of the invention.

Figure IB is a cross-sectional illustration of the RF switch in Figure 1A along line B-B', according to an embodiment of the invention.

Figure 1C is a plan view illustration of an RF switch with a spiral shaped resistor, according to an embodiment of the invention.

Figure 2Α is a plan view illustration of an RF switch being fabricated after a dummy gate electrode layer has been deposited over the exposed surfaces, according to an embodiment of the invention.

Figure 2B is a cross-sectional illustration along line B-B' in Figure 2Α, according to an embodiment of the invention.

Figure 3Α is a plan view illustration of the RF switch in Figure 2Α after the dummy gate electrode layer is patterned to form a resistor mask and a dummy gate electrode, according to an embodiment of the invention.

Figure 3B is a cross-sectional illustration of the RF switch in Figure 3 A along line B-B', according to an embodiment of the invention.

Figure 4A is a plan view illustration of the RF switch in Figure 3A after an interlayer dielectric is deposited and planarized to be substantially coplanar with top surfaces of the resistor mask and the dummy gate electrode, according to an embodiment of the invention.

Figure 4B is a cross-sectional illustration of the RF switch in Figure 4A along line B-B', according to an embodiment of the invention.

Figure 5A is a plan view illustration of the RF switch in Figure 4A after a second mask is formed over the resistor mask, according to an embodiment of the invention.

Figure 5B is a cross-sectional illustration of the RF switch in Figure 5A along line B-B', according to an embodiment of the invention.

Figure 6A is a plan view illustration of the RF switch in Figure 5A after the dummy gate electrode is removed, according to an embodiment of the invention.

Figure 6B is a cross-sectional illustration of the RF switch in Figure 6A along line B-B', according to an embodiment of the invention.

Figure 7A is a cross-sectional illustration of the RF switch in Figure 6A after the gate electrode is formed and planarized to be substantially coplanar with top surfaces of the interlayer dielectric and the resistor mask, according to an embodiment of the invention.

Figure 7B is a cross-sectional illustration of the RF switch in Figure 7A along line B-B', according to an embodiment of the invention.

Figure 8 is a cross-sectional illustration of an interposer implementing one or more embodiments of the invention.

Figure 9 is a schematic of a computing device that includes one or more transistors built in accordance with an embodiment of the invention.

DETAILED DESCRIPTION OF THE INVENTION

Described herein are systems that include a semiconductor device and methods for forming the semiconductor device that includes RF switches that include a gate electrode that is electrically isolated from the source and drain by a resistor. In the following description, various aspects of the illustrative implementations will be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art.

However, it will be apparent to those skilled in the art that the present invention may be practiced with only some of the described aspects. For purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the illustrative implementations. However, it will be apparent to one skilled in the art that the present invention may be practiced without the specific details. In other instances, well-known features are omitted or simplified in order not to obscure the illustrative implementations. Various operations will be described as multiple discrete operations, in turn, in a manner that is most helpful in understanding the present invention, however, the order of description should not be construed to imply that these operations are necessarily order dependent. In particular, these operations need not be performed in the order of presentation.

As noted above, RF transistors with a high switching frequency are needed to provide high data rate systems (e.g., 5G and above). In such systems the signal between the drain and the source of the transistor may be switched at a frequency of approximately 3.5 GHz and above. However, the switching speed of the gate electrode may be at a much lower frequency. For example, the gate electrode may be switched on and off at periods in the microsecond range (e.g., frequencies in the kHz and MHz range). The different orders of magnitude between the drain to source signal and the switching frequency of the gate electrode results in unwanted coupling between the two signals. The coupling diminishes the performance of the RF transistor and its functionality as a switch. In order to minimize and isolate the low frequency signal of the gate electrode, embodiments include isolating the gate electrode. In one embodiment, the gate electrode is isolated from the drain to source signaling by electrically coupling a resistor to the gate electrode.

Further embodiments of the invention include forming the resistor in parallel with a process flow used to form a replacement metal gate (RMG) transistor. Accordingly,

embodiments of the invention allow for the formation of a high performance RF switch that has reduced parasitic coupling without increasing the complexity of the fabrication process.

Referring now to Figures 1A and IB, a plan view illustration and a partial cross-sectional illustration along line B-B' are shown, respectively, according to an embodiment of the invention. Embodiments of the invention may include one or more RF switches 110. In an embodiment, the RF switch 110 may include a transistor portion 115 and an isolation portion 117. The RF switch 110 may be formed on a substrate 104, such as a semiconductor substrate. In one embodiment, the semiconductor substrate 104 may be a crystalline substrate formed using a bulk semiconductor or a semiconductor-on-insulator substructure. In one particular

embodiment, the semiconductor substrate 104 may include a stack of semiconductor materials. For example, the semiconductor substrate 104 may include a silicon base layer and one or more III-V semiconductor materials grown over the silicon base layer. In one example, a GaN layer may be the active device layer 142 and may be separated from the silicon base layer by one or more buffer layers (not shown in Figures IB). Embodiments may also include a polarization layer 143 formed at the top surface of the active device layer 142. In an embodiment where the active device layer is GaN, the polarization layer 143 may be A1N. In other embodiments, the semiconductor substrate may be formed using alternate materials, which may or may not be combined with silicon, that include but are not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, indium gallium arsenide, gallium antimonide, or other combinations of group III-V or group IV materials. Although a few examples of materials from which the substrate 104 and active device layer 142 may be formed are described here, any material that may serve as a foundation upon which a semiconductor device may be built falls within the spirit and scope of the present invention. In an embodiment, an insulating layer 105 may be formed over the surface of the substrate 104. The insulating layer 105 may contact and surround the device layer 142 to electrically isolate the RF switch 110 from neighboring RF switches 110. According to an embodiment, the isolation layer 105 may be any oxide, such as a silicon dioxide.

While a single RF switch 110 is illustrated in Figure 1, embodiments of the invention include forming a plurality of RF transistors, such as metal-oxide-semiconductor field-effect transistors (MOSFET or simply MOS transistors) on the substrate. Each RF switch 110 includes a gate stack formed of at least two layers, a gate dielectric layer 125 and a gate electrode layer 126. The gate dielectric layer 125 may include one layer or a stack of layers. The one or more layers may include silicon oxide, silicon dioxide (Si0 ₂ ) and/or a high-k dielectric material. The high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric layer 125 include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be carried out on the gate dielectric layer 125 to improve its quality when a high-k material is used.

In an embodiment, the gate electrode 126 may be separated from the gate dielectric layer 125 by at least one workfunction metal 127 (i.e., a P-type workfunction metal 127 or N-type workfunction metal 127, depending on whether the transistor is to be a PMOS or an NMOS transistor). In some embodiments, the gate electrode 126 may be considered a fill metal layer. In one embodiment, the gate electrode 126 may be tungsten.

For a PMOS transistor, metals that may be used for the workfunction metal 127 may include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, e.g., ruthenium oxide. A P-type metal layer will enable the formation of a PMOS gate electrode with a workfunction that is between about 4.9 eV and about 5.2 eV. For an NMOS transistor, metals that may be used for the workfunction metal include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide. An N-type metal layer will enable the formation of an NMOS gate electrode with a workfunction that is between about 3.9 eV and about 4.2 eV. In a particular embodiment of the invention, the workfunction metal 127 may be titanium nitride.

As is well known in the art, source regions 122 and drain regions 124 are formed within the substrate 104 on opposite ends of the gate electrode 126 of each switch 110. The source and drain regions 122/124 are generally formed using either an implantation/diffusion process or an etching/deposition process. In the former process, dopants such as silicon (for forming N-type GaN devices) or magnesium (for forming P-type GaN devices) may be ion-implanted into the substrate to form the source and drain regions. An annealing process that activates the dopants and causes them to diffuse further into the substrate typically follows the ion implantation process. In the latter process, the substrate 104 may first be etched to form recesses at the locations of the source and drain regions 122/124. An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the source and drain regions 122/124 . In some embodiments, the epitaxially deposited source and drain regions 122/124 may be doped in situ with dopants. In further embodiments, the source and drain regions 122/124 may be formed using a semiconductor material that is different than the semiconductor material used in the active layer 142 of the transistor channel.

While not shown in Figure 1A and IB in order to not obscure the details of the Figures, embodiments may include one or more interlayer dielectrics (ILD) deposited over the RF switches 110. The ILD layers may be formed using dielectric materials known for their applicability in integrated circuit structures, such as low-k dielectric materials. Examples of dielectric materials that may be used include, but are not limited to, silicon dioxide (Si0 ₂ ), carbon doped oxide (CDO), silicon nitride, organic polymers such as perfluorocyclobutane or polytetrafluoroethylene, fluorosilicate glass (FSG), and organosilicates such as silsesquioxane, siloxane, or organosilicate glass. The ILD layers may include pores or air gaps to further reduce their dielectric constant.

In order to isolate the gate electrode 126 from the high frequency signaling between the source 122 and drain 124, embodiments of the invention include an isolation region 117 formed over the substrate 104. In an embodiment, the isolation region 117 includes a resistor 158 that is electrically coupled to the gate electrode 126. In an embodiment, the resistor 158 is coupled to the gate electrode 126 by the workfunction metal 127. More specifically, the resistor 158 may be formed from the same material layer that the workfunction metal 127 is formed from, as will be described in greater detail below. Accordingly, since the workfunction metal 127 and the resistor 158 are formed from the same layer, embodiments of the invention include a resistor 158 that has substantially the same thickness T as the workfunction metal 127. In an embodiment, the resistor 158 may also be formed above portions of the gate dielectric layer 125. In an embodiment, a resistor mask layer 156 may be formed over a top surface of the resistor 158. The resistor mask 156 may be the same material used to form the dummy gate electrode in an RMG process, as will be described in greater detail below. For example, the resistor mask 156 may be polysilicon. In an embodiment, the polysilicon may be intrinsic, doped N-type (e.g., with dopants such as, phosphorus, arsenic, etc.), or doped P-type (e.g., with dopants such as boron or the like). In addition to serving as a mask layer used to pattern the resistor 158, embodiments may also utilize the resistor mask 156 as a temperature stabilization component in order to stabilize the resistivity of the resistor (which may be temperature dependent) as the temperature fluctuates during operation.

The resistance of the resistor 158 may be set by controlling the geometry of the resistor 158. For example, the overall length of the resistor 158 between the gate electrode 126 and the gate contact 129 may be increased or decreased to provide the desired resistance. Embodiments of the invention may include a serpentine patterned resistor 158 in order to increase the length of the resistor without significantly increasing the footprint of the resistor 158. While a serpentine pattern is shown in Figure 1A, it is to be appreciated that the resistor 158 may be any pattern. For example, Figure 1C is a plan view illustration of an RF switch 110 that is substantially similar to the RF switch 110 in Figure 1A, with the exception that the resistor 158 includes a spiral pattern instead of a serpentine pattern. Additionally, the cross-sectional area of the resistor 158 may be modified to provide the desire resistance. For example, the width W of the resistor 158 may be increased or decreased to provide the desired resistance. In an embodiment, the resistor 158 may have a resistance that is approximately 50 kQ or greater. In an additional embodiment, the resistor 158 may have a resistance that is between approximately 50 kQ and 2500 kQ.

In an embodiment, the RF switch 110 may be formed with an RMG process. In such an embodiment, the resistor 158 in the isolation region 117 may be formed using the same patterning masks used in the RMG process. As such, additional patterning is not needed and manufacturing costs are not significantly increased. Figures 2A-7B, are a series of plan view illustrations and corresponding cross-sectional illustrations of a process for forming an RF switch with a resistor, according to an embodiment. Referring now to Figure 2A and 2B, a plan view illustration and a corresponding cross- sectional illustration along line B-B' are shown, respectively, according to an embodiment of the invention. In Figure 2A the source and drain regions 122/124 are shown as already being formed. However, embodiments of the invention may also include forming the source and drain regions 122/124 in subsequent processing operations instead. For example, the source and drain regions 122/124 may be formed after the dummy gate electrode is formed.

In an embodiment, the gate dielectric 125 and the workf unction metal 127 may be blanket deposited over the active region 142 and the insulating layer 105. Additionally, a dummy gate layer 262 may be blanket deposited over the workfunction metal 127. In an embodiment, the dummy gate layer 262 may be polysilicon. According to an embodiment, the dummy gate layer 262 may be deposited with any suitable deposition process, such as plasma enhanced chemical vapor deposition (PECVD), or the like.

Referring now to Figure 3A and 3B, a plan view illustration and a corresponding cross- sectional illustration along line B-B' after the dummy gate layer 262 is patterned are shown, respectively, according to an embodiment of the invention. In an embodiment, the dummy gate layer 262 may be patterned with a single lithography mask to form both a dummy gate electrode 356 and the resistor mask 156. For example, a photosensitive resist may be deposited over the dummy gate layer 262 and exposed with the lithography mask. The exposed resist may then be developed, and the exposed regions of the dummy gate layer 262 may be etched away with any suitable etching process known in the art. In an embodiment, the etching process may also be used to remove at least the workfunction metal 127 from the exposed regions, thereby defining the pattern of the resistor 158. In the illustrated embodiment, a serpentine patterned resistor 158 is shown, though embodiments of the invention my include any desired pattern (e.g., a spiral pattern) and the resistor 158 may have any length or width to provide a desired resistance. In an embodiment, the patterning process may also include removing the gate dielectric layer 125 in the exposed regions. In an alternative embodiment, the blanket deposited gate dielectric layer 125 may not be etched and remain behind in the final structure as a blanket layer. In an embodiment, a single etching chemistry may be used to remove one or more of the dummy gate layer 262, the exposed regions of the workfunction metal 127, and the exposed regions of the gate dielectric 125. Additional embodiments may include removing each of the layers with a different etching chemistry.

Referring now to Figures 4A and 4B, a plan view illustration and a corresponding cross- sectional illustration along line B-B' after an ILD 455 is formed are shown, respectively, according to an embodiment of the invention. In an embodiment, an ILD 455 may be deposited and planarized so that top surfaces of the dummy gate electrode 356 and the resistor mask 156 are substantially coplanar with the ILD 455. For example, the ILD 455 may be deposited with any deposition process typically used for depositing ILDs, such as PECVD, or the like. In an embodiment, the ILD 455 may be a material that is etch selective to the material used to form the dummy gate electrode 356 and the resistor mask 156. In an embodiment, the ILD 455 may be planarized with a polishing process, such as chemical mechanical polishing (CMP). The ILD 455 may cover the surface of the source and drain regions 122/124. Accordingly, for purposes of clarity, the source and drain regions 122/124 are represented with dashed lines in Figure 4 A to indicate that the source and drain regions 122/124 are formed below the ILD 455.

At this point in the process flow, the dummy gate electrode 356 and the resistor mask 156 are formed as a single continuous material layer. Since the two regions are formed from the same material, it is not possible to selectively etch one region over the other without providing an etch mask to protect the resistor mask 156. Accordingly, in order to selectively remove the dummy gate electrode 356 while leaving the resistor mask in place, embodiments include forming a second mask over the resistor mask 156.

Referring now to Figures 5 A and 5B, a plan view illustration and a corresponding cross- sectional illustration along line B-B' after a second mask 557 is formed over the isolation region 117 are shown, respectively, according to an embodiment. Embodiments include forming a second mask 557 over the isolation region 117 in order to protect the resistor mask 156 and the resistor 158 from subsequent patterning used to form the gate electrode 356. In an embodiment, the second mask 557 may be a photosensitive resist. For example, the photosensitive resist may be formed over the ILD 455, the dummy gate electrode 356, and the resistor mask 156.

Thereafter, the photosensitive resist may be exposed and developed, leaving behind the second mask 557 over only the isolation region 117 where the resistor mask 156 is formed. Accordingly, the dummy gate electrode 356 may be exposed. Additionally, an end portion of the resistor mask 156 opposite from the end connected to the dummy gate electrode 356 may be exposed in order to form a gate contact opening. While a photosensitive resist is described as being used for the second mask 557, it is to be appreciated that any type of mask layer may be used to shield the resistor mask 156. For example, a patterned hardmask may be formed over the resistor mask instead of a photosensitive resist, according to an additional embodiment of the invention.

Referring now to Figure 6A and 6B, a plan view illustration and a corresponding cross- sectional illustration along line B-B' after the dummy gate electrode 356 is removed are shown, respectively, according to an embodiment of the invention. In an embodiment, the dummy gate electrode may be removed with an etching process, such as a wet or dry etching process. In an embodiment, the etching process may substantially remove the dummy gate electrode 356 and expose the underlying workfunction metal 127. Removing the dummy gate electrode 356 produces a gate opening 662 defined by the ILD 455 in which the gate electrode may be deposited in a subsequent processing operation. In some embodiments, the dummy gate contact may also be removed to form a gate contact opening 663 through the ILD 455. After the gate electrode opening 662 and gate contact opening 663 are formed, embodiments of the invention may include removing the second mask 557. In embodiments where the second mask 557 is a photosensitive resist, the second mask 557 may be removed with an ashing process. In an embodiment where the second mask 557 is a hardmask, the second mask 557 may be removed with an etching process that is selective to the second mask 557 over the ILD 455 and the resistor mask 156.

Referring now to Figure 7A and 7B, a plan view illustration and a corresponding cross- sectional illustration along line B-B' after the gate electrode 126 is deposited into the gate opening 662 are shown, respectively, according to an embodiment of the invention. In an embodiment, the gate electrode 126 may be deposited with any suitable process, such as CVD, PECVD, physical vapor deposition (PVD), or the like. In an embodiment, deposition of the gate electrode 126 may also include depositing a gate contact 129 in the gate contact opening 663. Accordingly, the gate electrode 126 and the gate contact 129 may be the same material. In an embodiment, excess metal deposited above the top of the openings and over the ILD 455 and the resistor mask 156 may be recessed so that the gate electrode 126 and the gate contact 129 are substantially coplanar with a top surface of the ILD 455. For example, a CMP process may be used to planarize the excess conductive material.

Figure 8 illustrates an interposer 800 that includes one or more embodiments of the invention. The interposer 800 is an intervening substrate used to bridge a first substrate 802 to a second substrate 804. The first substrate 802 may be, for instance, an integrated circuit die. The second substrate 804 may be, for instance, a memory module, a computer motherboard, or another integrated circuit die. Generally, the purpose of an interposer 800 is to spread a connection to a wider pitch or to reroute a connection to a different connection. For example, an interposer 800 may couple an integrated circuit die to a ball grid array (BGA) 806 that can subsequently be coupled to the second substrate 804. In some embodiments, the first and second substrates 802/804 are attached to opposing sides of the interposer 800. In other embodiments, the first and second substrates 802/804 are attached to the same side of the interposer 800. And in further embodiments, three or more substrates are interconnected by way of the interposer 800. The interposer 800 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In further implementations, the interposer may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials.

The interposer may include metal interconnects 808 and vias 810, including but not limited to through- silicon vias (TSVs) 812. The interposer 800 may further include embedded devices 814, including both passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices such as radio-frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the interposer 800.

In accordance with embodiments of the invention, apparatuses that include RF switches with an isolation resistor, or processes for forming such devices disclosed herein may be used in the fabrication of interposer 800.

Figure 9 illustrates a computing device 900 in accordance with one embodiment of the invention. The computing device 900 may include a number of components. In one embodiment, these components are attached to one or more motherboards. In an alternate embodiment, these components are fabricated onto a single system-on-a-chip (SoC) die rather than a motherboard. The components in the computing device 900 include, but are not limited to, an integrated circuit die 902 and at least one communication chip 908. In some implementations the communication chip 908 is fabricated as part of the integrated circuit die 902. The integrated circuit die 902 may include a CPU 904 as well as on-die memory 906, often used as cache memory, that can be provided by technologies such as embedded DRAM (eDRAM) or spin-transfer torque memory (STTM or STTM-RAM).

Computing device 900 may include other components that may or may not be physically and electrically coupled to the motherboard or fabricated within an SoC die. These other components include, but are not limited to, volatile memory 910 (e.g., DRAM), non- volatile memory 912 (e.g., ROM or flash memory), a graphics processing unit 914 (GPU), a digital signal processor 916, a crypto processor 942 (a specialized processor that executes cryptographic algorithms within hardware), a chipset 920, an antenna 922, a display or a touchscreen display 924, a touchscreen controller 926, a battery 928 or other power source, a power amplifier (not shown), a global positioning system (GPS) device 944, a compass 930, a motion coprocessor or sensors 932 (that may include an accelerometer, a gyroscope, and a compass), a speaker 934, a camera 936, user input devices 938 (such as a keyboard, mouse, stylus, and touchpad), and a mass storage device 940 (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).

The communications chip 908 enables wireless communications for the transfer of data to and from the computing device 900. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non- solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip 908 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev- DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing device 900 may include a plurality of communication chips 908. For instance, a first communication chip 908 may be dedicated to shorter range wireless

communications such as Wi-Fi and Bluetooth and a second communication chip 908 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

The processor 904 of the computing device 900 includes one or more devices, such as RF switches with an isolation resistor, or processes for forming such devices, according to an embodiment of the invention. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

The communication chip 908 may also include one or more devices, such as RF switches with an isolation resistor, or processes for forming such devices, according to an embodiment of the invention.

In further embodiments, another component housed within the computing device 900 may contain one or more devices, such as RF switches with an isolation resistor, or processes for forming such devices, according to an embodiment of the invention.

In various embodiments, the computing device 900 may be a laptop computer, a netbook computer, a notebook computer, an ultrabook computer, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device 900 may be any other electronic device that processes data.

The above description of illustrated implementations of the invention, including what is described in the Abstract, is not intended to be exhaustive or to limit the invention to the precise forms disclosed. While specific implementations of, and examples for, the invention are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the invention, as those skilled in the relevant art will recognize.

These modifications may be made to the invention in light of the above detailed description. The terms used in the following claims should not be construed to limit the invention to the specific implementations disclosed in the specification and the claims. Rather, the scope of the invention is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.

Example 1: An RF switch comprising: a semiconductor substrate; a transistor region formed over the semiconductor substrate, wherein the transistor region comprises: a source; a drain; and a gate electrode formed between the source and the drain; and an isolation region formed over the substrate, wherein the isolation region comprises: a resistor electrically coupled to the gate electrode.

Example 2: the RF switch of Example 1, wherein the gate electrode is separated from the substrate by a gate dielectric and a workfunction metal.

Example 3: the RF switch of Example 2, wherein the workfunction metal and the resistor are the same thickness.

Example 4: the RF switch of Example 2 or Example 3, wherein the workfunction metal and the resistor are the same conductive material.

Example 5: the RF switch of Example 1, Example 2, Example 3, or Example 4, wherein the isolation region further comprises: a resistor mask formed over a top surface of the resistor.

Example 6: the RF switch of Example 2, Example 3, Example 4, or Example 5, wherein a bottom surface of the resistor contacts the gate dielectric.

Example 7: the RF switch of Example 5, or Example 6, wherein the resistor mask is an intrinsic polysilicon, an N-doped polysilicon, or a P-doped polysilicon.

Example 8: the RF switch of Example 1, Example 2, Example 3, Example 4, Example 5, Example 6, or Example 7, wherein the resistor is formed in a serpentine pattern.

Example 9: the RF switch of Example 1, Example 2, Example 3, Example 4, Example 5, Example 6, or Example 7, wherein the resistor is formed in a spiral pattern.

Example 10: the RF switch of Example 1, Example 2, Example 3, Example 4, Example 5, Example 6, Example 7, Example 8, or Example 9, wherein the resistance of the resistor is greater than approximately 50 kQ.

Example 11: the RF switch of Example 1, Example 2, Example 3, Example 4, Example 5, Example 6, Example 7, Example 8, Example 9, or Example 10, wherein the resistance of the resistor is between approximately 50 kQ and 250 kQ

Example 12: he RF switch of Example 1, Example 2, Example 3, Example 4, Example 5,

Example 6, Example 7, Example 8, Example 9, Example 10, or Example 11, further comprising: a gate contact formed on an end of the resistor opposite from an end of the resistor contacting the gate electrode.

Example 13: the RF switch of Example 12, wherein the gate contact and the gate electrode are the same material.

Example 14: A method of forming an RF switch, comprising: depositing a gate dielectric layer over a semiconductor substrate; depositing a workfunction metal over the gate dielectric layer; depositing a dummy gate electrode layer over the workfunction metal; patterning the dummy gate electrode layer with a single patterning mask to form a dummy gate electrode and a resistor mask, wherein the dummy gate electrode and the resistor mask are attached together as a single layer; removing exposed portions of the workfunction metal to define a resistor underneath the resistor mask, wherein the resistor is formed from the workfunction metal;

depositing an interlayer dielectric (ILD) over the semiconductor substrate, wherein a top surface of the ILD is substantially coplanar with top surfaces of the dummy gate electrode and the resist mask; removing the dummy gate electrode to form a gate electrode opening defined by the ILD; and depositing a gate electrode into the gate electrode opening.

Example 15: the method of Example 14, wherein removing the dummy gate electrode comprises: forming a second mask over the resistor mask prior to removing the dummy gate electrode.

Example 16: the method of Example 15, wherein the second mask is a photosensitive resist or a hardmask material.

Example 17: the method of Example 14, Example 15, or Example 16, further comprising: removing exposed portions of the gate dielectric layer after removing the exposed portions of the workfunction metal.

Example 18: the method of Example 14, Example 15, Example 16, or Example 17, wherein the resistor mask is in a serpentine pattern.

Example 19: the method of Example 14, Example 15, Example 16, or Example 17, wherein the resistor mask is in a spiral pattern.

Example 20: the method of Example 14, Example 15, Example 16, Example 17, Example 18, or Example 19, wherein the dummy gate layer is an intrinsic polysilicon, an N-doped polysilicon, or a P-doped polysilicon.

Example 21: the method of Example 14, Example 15, Example 16, Example 17, Example 18, Example 19, or Example 20, wherein the resistor has a resistance greater than approximately 50 kQ.

Example 22: the method of Example 14, Example 15, Example 16, Example 17, Example 18, Example 19, Example 20, or Example 21, wherein the resistor has a resistance between approximately 50 kQ and 250 kQ.

Example 23: An RF switch comprising: a semiconductor substrate, wherein an active device layer of the semiconductor substrate is GaN; a transistor region formed over the semiconductor substrate, wherein the transistor region comprises: a source; a drain; and a gate electrode formed between the source and the drain, wherein the gate electrode is separated from the active device layer by a gate dielectric and a workfunction metal; and an isolation region formed over the substrate, wherein the isolation region comprises: a resistor electrically coupled to the gate electrode by the workfunction metal, wherein the resistor is formed in the same layer as the workfunction metal, and wherein a first end of the resistor contacts the gate electrode and a second end of the resistor contacts a gate electrode contact; and a resistor mask formed over the resistor, wherein the resistor mask is an intrinsic polysilicon, an N-doped polysilicon, or a P- doped polysilicon.

Example 24: the RF switch of Example 23, wherein the resistor is formed in a serpentine pattern or a spiral pattern.

Example 25: the RF switch of Example 23 or Example 24, wherein the resistor has a resistance between approximately 50 kQ and 250 kQ.