CACHE MEMORY SYSTEMS

PRIORITY CLAIM

[0001] The present application claims priority under 35 U.S.C. § 119(e) to U.S. Provisional Patent Application Serial No. 62/084,469 filed on November 25, 2014, and entitled "GENERATING APPROXIMATE USAGE MEASUREMENTS FOR SHARED CACHE MEMORY, AND RELATED METHODS AND SYSTEMS," the contents of which is incorporated herein by reference in its entirety.

[0002] The present application also claims priority to U.S. Patent Application Serial No. 14/860,993 filed on September 22, 2015, and entitled "GENERATING APPROXIMATE USAGE MEASUREMENTS FOR SHARED CACHE MEMORY SYSTEMS," the contents of which is incorporated herein by reference in its entirety.

BACKGROUND

I. Field of the Disclosure

[0003] The technology of the disclosure relates generally to shared cache memory systems, and, in particular, to measuring usage of shared caches.

II. Background

[0004] An increasing number of computer hardware units (e.g., central processing units (CPUs), graphics processing units (GPUs), digital signal processing (DSP) units, and/or direct memory access (DMA) engines, as non- limiting examples) are configured to share memory system resources such as caches, memory, interconnect bandwidth, and cache bandwidth. Resource interference and conflicts between computer hardware units could result in negative consequences, such as missing a real-time deadline on a mobile System-on- Chip (SoC), or violating a Service Level Agreement (SLA) on a consolidated server, as non- limiting examples. Additionally, reference streams associated with some computer hardware units may have little temporal locality, leading to cache pollution and a negative impact on overall performance if left unchecked. Accordingly, monitoring the effects of resource sharing has become more important to achieving optimal system performance. In this regard, it may be desirable for users to have the ability to monitor the usage of shared resources.

[0005] However, conventional cache memory systems do not provide a space-efficient mechanism for monitoring cache usage. As a result, such conventional cache memory systems may remain underutilized to protect against worst case performance in the presence of cache interference. Moreover, a lack of feedback regarding cache occupancy may result in computer processing systems being unable to provide optimal scheduling of system tasks.

SUMMARY OF THE DISCLOSURE

[0006] Aspects disclosed in the detailed description include generating approximate usage measurements for shared cache memory systems. In this regard, in one aspect, a shared cache memory system is provided. The shared cache memory system is configured to approximate cache usage for each of a plurality of Quality of Service (QoS) classes, each QoS class having an associated QoS identifier (QoSID). The shared cache memory system includes a plurality of cache lines that are subdivided into a plurality of cache subdivisions. According to some aspects disclosed herein, the plurality of cache subdivisions may comprise individual cache lines, sets of cache lines, and/or banks of cache lines, as non-limiting examples. The plurality of cache subdivisions are each associated with one of the plurality of QoS classes for which cache usage is to be approximated. The shared cache memory system also provides a plurality of QoSID tracking tags corresponding to the plurality of cache subdivisions. Upon receiving a memory access request comprising a QoSID, a cache usage monitor of the shared cache memory system is further configured to access a cache subdivision corresponding to the memory access request. The cache usage monitor is configured to determine whether the QoSID of the memory access request corresponds to a QoS class associated with the cache subdivision. Based on this determination, the cache usage monitor updates a QoSID tracking tag associated with the cache subdivision corresponding to the memory access request. In this manner, the plurality of QoSID tracking tags may be maintained to indicate whether a QoS class associated with each cache subdivision is actually using that cache subdivision at a given time.

[0007] The cache usage monitor is further configured to generate an approximate usage measurement for a QoS class of the plurality of QoS classes based on the plurality of QoSID tracking tags. By trading off accuracy of the cache usage measurement for a reduction in storage overhead for the plurality of QoSID tracking tags, the shared cache memory system may provide sufficient usage measurement data for managing cache allocation, while minimizing impacts on processor performance and power consumption.

[0008] In another aspect, a shared cache memory system is provided. The shared cache memory system comprises a plurality of cache subdivisions. The shared cache memory system further comprises a plurality of QoSID tracking tags each associated with a cache subdivision of the plurality of cache subdivisions. The shared cache memory system also comprises a cache usage monitor. The cache usage monitor is configured to associate each cache subdivision of the plurality of cache subdivisions with a QoS class of a plurality of QoS classes. The cache usage monitor is further configured to receive a memory access request comprising a QoSID. The cache usage monitor is also configured to access a cache subdivision corresponding to the memory access request among the plurality of cache subdivisions. The cache usage monitor is additionally configured to determine whether the QoSID of the memory access request corresponds to the QoS class associated with the cache subdivision. The cache usage monitor is further configured to update a QoSID tracking tag plurality of QoSID tracking tags associated with the cache subdivision corresponding to the memory access request based on the determination. The cache usage monitor is also configured to generate an approximate usage measurement for the QoS class of the plurality of QoS classes based on the plurality of QoSID tracking tags.

[0009] In another aspect, a shared cache memory system is provided. The shared cache memory system comprises a means for associating each cache subdivision of a plurality of cache subdivisions of the shared cache memory system with a QoS class of a plurality of QoS classes. The shared cache memory system further comprises a means for receiving a memory access request comprising a QoSID. The shared cache memory system also comprises a means for accessing a cache subdivision corresponding to the memory access request among the plurality of cache subdivisions. The shared cache memory system additionally comprises a means for determining whether the QoSID of the memory access request corresponds to the QoS class plurality of QoS classes associated with the cache subdivision. The shared cache memory system further comprises a means for updating a QoSID tracking tag of a plurality of QoSID tracking tags associated with the cache subdivision corresponding to the memory access request based on the means for determining. The shared cache memory system also comprises a means for generating an approximate usage measurement for the QoS class of the plurality of QoS classes based on the plurality of QoSID tracking tags.

[0010] In another aspect, a method for approximating shared cache memory usage is provided. The method comprises associating each cache subdivision of a plurality of cache subdivisions of a shared cache memory system with a QoS class of a plurality of QoS classes. The method further comprises receiving a memory access request comprising a QoSID. The method also comprises accessing a cache subdivision corresponding to the memory access request among the plurality of cache subdivisions. The method additionally comprises determining whether the QoSID of the memory access request corresponds to the QoS class plurality of QoS classes associated with the cache subdivision. The method further comprises updating a QoSID tracking tag of a plurality of QoSID tracking tags associated with the cache subdivision corresponding to the memory access request based on the determining. The method also comprises generating an approximate usage measurement for the QoS class of the plurality of QoS classes based on the plurality of QoSID tracking tags.

BRIEF DESCRIPTION OF THE FIGURES

[0011] Figure 1 illustrates an exemplary shared cache memory system including a cache controller comprising a cache usage monitor for generating approximate usage measurements for the shared cache memory system;

[0012] Figures 2A-2D illustrate exemplary shared cache memory system implementations wherein Quality of Service (QoS) classes and QoS identifier (QoSID) tracking tags are associated with cache subdivisions comprising cache lines, sets of cache lines, and banks of cache lines, respectively;

[0013] Figures 3A and 3B illustrate exemplary operations of the shared cache memory system of Figure 1 for generating approximate usage measurements for the shared cache memory system; and

[0014] Figure 4 is a block diagram of an exemplary processor-based system that can include the shared cache memory system of Figure 1 to provide approximate usage measurements.

DETAILED DESCRIPTION

[0015] With reference now to the drawing figures, several exemplary aspects of the present disclosure are described. The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects.

[0026] In this regard, Figure 1 is provided to illustrate a structure of a shared cache memory system 100. The shared cache memory system 100 may be provided in a semiconductor die, as a non-limiting example. In some aspects, the shared cache memory system 100 may be a level 1 (LI) cache, a level 2 (L2) cache, or a level 3 (L3) cache, among others, in a hierarchy of memories (not shown). In the example of Figure 1, the shared cache memory system 100 is a memory array organized into banks 102(0)-102(X). Each of the banks 102(0)-102(X) comprises one or more sets 104(0)-104(Y), with each of the sets 104(0)- 104(Y) made up of a subset of cache lines 106(0)- 106(L). The number Z of the cache lines 106(0)-106(L) in each of the sets 104(0)-104(Y) is referred to as the "associativity" of the shared cache memory system 100, and the group of cache lines 106(0)- 106(L) located at a particular position from 0-Z within each of the sets 104(0)- 104(Y) is referred to as a corresponding "way" 108(0)- 108(Z). Each way 108(0)- 108(Z) may thus be visualized as a vertical "slice" of the cache lines 106(0)-106(L) across all of the sets 104(0)- 104(Y).

[0027] It is to be understood that aspects described herein are not restricted to any particular arrangement of elements, and the disclosed techniques may be easily extended to various structures and layouts of the shared cache memory system 100. The configuration illustrated in Figure 1 is for illustrative purposes only. In some aspects, the shared cache memory system 100 may comprise fewer or more banks 102(0)- 102(X), fewer or more sets 104(0)- 104(Y), fewer or more cache lines 106(0)-106(L), and/or fewer or more ways 108(0)- 108(Z) than illustrated herein.

[0030] With continued reference to Figure 1, a cache controller 110 is coupled to each bank 102(0)- 102(X). In conventional operation, a requesting agent (not shown), such as an executing software application, may request an instruction or value (not shown) stored at a memory address (not shown). If the requested instruction or value is not found in the shared cache memory system 100, a cache miss results. In response, the cache controller 110 may initiate a cache fill operation, which causes a portion of system memory (not shown) equal to the size of one or more of the cache lines 106(0)-106(L), and containing the requested instruction or value, to be retrieved and stored in one of the cache lines 106(0)-106(L).

[0031] The shared cache memory system 100 provides support for multiple QoS classes 112(0)-112(N) for implementing QoS support for shared memory usage. Each of the QoS classes 112(0)-112(N) is associated with a unique QoSID 114(0)-114(N). To more efficiently allocate the cache lines 106(0)- 106(L) among multiple requesting agents, the cache controller 110 in some aspects may provide a cache allocation circuit 116. The cache allocation circuit 116 may enable user control of cache resources of the shared cache memory system 100 by associating each of the QoSIDs 114(0)-114(N) with a particular requesting agent, and specifying an allocation of the cache lines 106(0)- 106(L) for that QoSID 114(0)- 114(N). [0032] By allocating the cache lines 106(0)-106(L) among the QoSIDs 114(0)-114(N) (thus effectively allocating the cache lines 106(0)- 106(L) among the corresponding QoS classes 112(0)-112(N)), the shared cache memory system 100 may improve cache performance in a number of use case scenarios. For example, in some aspects, the shared cache memory system 100 may enable real-time constraints to ensure that latency-critical operations carried out by requesting agents have sufficient cache memory to satisfy real-time requirements. To provide service responsive to real-time constraints, the cache allocation circuit 116 may be configured to guarantee that a minimum working set of the cache lines 106(0)- 106(L) for a time-critical requesting agent will be preserved in the shared cache memory system 100. Allocation of the cache lines 106(0)- 106(L) by the cache allocation circuit 116 may also be useful in enforcing cloud computing Service Level Agreements (SLAs), and/or for restricting the cache allotment of the cache lines 106(0)-106(L) for certain requesting agents to improve the overall throughput of a computer processing system.

[0033] Efficient allocation of the cache lines 106(0)- 106(L) among multiple requesting agents involves monitoring the usage of the shared cache memory system 100 by different QoS classes 112(0)-112(N) in order to determine the effects of resource allocation on overall system performance. However, conventional cache memory systems do not provide a space- efficient mechanism for monitoring cache usage. To monitor how many of the cache lines 106(0)- 106(L) are used by a given QoS class 112(0)-112(N), the shared cache memory system 100 has the ability to identify those cache lines 106(0)- 106(L) that were accessed by each QoS class 112(0)-112(N).

[0034] One approach involves tagging each of the cache lines 106(0)- 106(L) with the QoSID 114(0)-114(N) of the QoS class 112(0)-112(N) to which the cache lines 106(0)- 106(L) are currently allocated. This approach, though, may be prohibitively expensive in terms of storage space within the shared cache memory system 100. For example, in a system that supports a number N of QoS classes 112(0)-112(N), each QoSID 114(0)-114(N) is nominally log ₂ (N) bits wide. For example, if the shared cache memory system 100 were 32 megabytes in size, comprising 128-byte lines tagged with 8-bit QoSIDs 114(0)-114(N), the QoSIDs 114(0)-114(N) would account for 256 kilobytes, which may be approximately the size of a conventional L2 cache in some computer processor cores.

[0035] In this regard, the shared cache memory system 100 reduces storage overhead by generating approximate usage measurements that are sufficiently accurate for use in determining and monitoring allocation of the cache lines 106(0)-106(L). The shared cache memory system 100 thus provides a cache usage monitor 118 to provide approximate usage measurements, such as approximate usage measurements 120 provided to the cache allocation circuit 116 of the cache controller 110. In some aspects, users (not shown) may query the cache usage monitor 118 using the QoSIDs 114(0)-114(N) to discover an approximation of the current cache usage of the corresponding QoS class 112(0)-112(N). In such aspects, the approximate usage measurements 120 may be provided through a memory- mapped interface (not shown), as a non- limiting example.

[0036] To provide space-efficient monitoring of cache usage, the cache usage monitor 118 in some aspects may associate each of a plurality of cache subdivisions of the cache lines 106(0)- 106(L) with one of the QoS classes 112(0)-112(N). According to some aspects, the plurality of cache subdivisions may comprise one or more of the cache lines 106(0)-106(L), the sets 104(0)- 104(Y) of the cache lines 106(0)- 106(L), the ways 108(0)-108(Z) of the cache lines 106(0)- 106(L), or the banks 102(0)-102(X) of the cache lines 106(0)- 106(L), as non- limiting examples. These exemplary implementations are discussed in greater detail below with respect to Figures 2A-2D. Each cache subdivision is also associated with one of a plurality of QoSID tracking tags (not shown), each of which may be used by the cache usage monitor 118 to track whether the cache subdivision is currently being used by the QoS class 112(0)-112(N) with which it is associated. According to some aspects, each of the plurality of QoSID tracking tags may comprise a single bit. In some aspects, the QoS tracking tag may comprise multiple bits, enabling each cache subdivision to be associated with multiple QoS classes 112(0)-112(N). In some aspects, the plurality of QoSID tracking tags may be stored inline with the cache lines 106(0)-106(L), while some aspects may provide that the plurality of QoSID tracking tags are stored in a QoSID tracking tag data structure 122. It is to be understood that, while Figure 1 illustrates the QoSID tracking tag data structure 122 as located within the cache controller 110, the QoSID tracking tag data structure 122 in some aspects may be located elsewhere within the shared cache memory system 100 (e.g., within the cache usage monitor 118, as a non-limiting example).

[0037] Upon receiving a memory access request 124 comprising a QoSID 126, the cache usage monitor 118 accesses the cache subdivision corresponding to the memory access request 124, and determines whether the QoSID 126 of the memory access request 124 corresponds to the QoS class 112(0)-112(N) associated with the cache subdivision. Based on this determination, the cache usage monitor 118 may update the QoSID tracking tag of the cache subdivision corresponding to the memory access request 124. For example, in some aspects providing one -bit QoSID tracking tags, if the QoSID 126 of the memory access request 124 corresponds to the QoS class 112(0)-112(N) associated with the cache subdivision, the cache usage monitor 118 may set the QoSID tracking tag of the cache subdivision to a value of one (1). If the QoSID 126 of the memory access request 124 does not correspond to the QoS class 112(0)-112(N) associated with the cache subdivision, the cache usage monitor 118 may set the QoSID tracking tag of the cache subdivision to a value of zero (0). In this manner, the QoSID tracking tags may be maintained to indicate whether the QoS class 112(0)-112(N) associated with each cache subdivision is actually using that cache subdivision at a given time.

[0038] Based on the QoSID tracking tags, the cache usage monitor 118 may generate the approximate usage measurements 120 of the cache lines 106(0)- 106(L) for each of the QoS classes 112(0)-112(N). In some aspects, the cache usage monitor 118 may generate the approximate usage measurements 120 by determining a fraction of the plurality of cache subdivisions associated with the QoS class 112(0)-112(N), and further determining a count of the cache subdivisions associated with the QoS class 112(0)-112(N) for which an associated QoSID tracking tag is set. The cache usage monitor 118 may then divide the count of the cache subdivisions by the fraction to generate the approximate usage measurements 120.

[0039] As a non- limiting example, assume that the shared cache memory system 100 provides sixteen (16) sets 104(0)-104(15) that represent the cache subdivisions. The sets 104(0)- 104(7), or half of the total number of sets 104(0)-104(15), are associated with the QoS class 112(0) for measurement purposes, while the sets 104(8)-104(15) are associated with the QoS class 112(N) for measurement purposes. Thus, the fraction of the plurality of cache subdivisions associated with each of the QoS classes 112(0) and 112(1), for instance, is ½, or 0.5. Assume further that six (6) of the sets 104(0)-104(5) that are associated with the QoS class 112(0) have an associated QoSID tracking tag that is set. Accordingly, the cache usage monitor 118 may generate an approximate usage measurement 120 that estimates that twelve (12) (i.e., six (6) divided by 0.5) of the sets 104(0)- 104(15) are currently in use by the QoS class 112(0).

[0040] In some aspects, the cache usage monitor 118 may improve its accuracy by associating the cache subdivisions only with active QoS classes 112(0)-112(N), rather than associating the cache subdivisions with a fixed maximum number of QoS classes 112(0)- 112(N). For example, if only one QoS class 112(0) is active, the active QoS class 112(0) may be associated with every cache line 106(0)-106(L) in the shared cache memory system 100, resulting in the approximate usage measurements 120 having zero error. Some aspects may provide that, in addition to reducing the number of bits needed to identify a QoS class 112(0)-112(N), the cache usage monitor 118 may also employ conventional sampling methods. As a non-limiting example, the QoSID tracking tags may be associated only with a distributed subset of the cache subdivisions.

[0041] The approximation techniques may be combined in some aspects to provide a configuration of the shared cache memory system 100 having an acceptable tradeoff between overhead and accuracy for a given application. The storage requirements for combinations provided in some aspects are illustrated in Table 1 below. In Table 1, the total storage, in bytes, required by various configurations is indicated. Each entry is calculated based on an 8 megabyte, 16-way, 128-byte-line, 4-bank cache, and a system that supports a maximum of 32 QoSIDs. The number in parentheses is the percentage of the relative overhead needed to fully and precisely track which cache line is appended with a 5-bit QoSID.

Table 1

[0042] As noted above, in some aspects, the cache subdivisions may comprise one or more of the cache lines 106(0)-106(L), the sets 104(0)-104(Y) of the cache lines 106(0)- 106(L), the ways 108(0)-108(Z) of the cache lines 106(0)- 106(L), or the banks 102(0)-102(X) of the cache lines 106(0)- 106(L). In this regard, Figures 2A-2D are provided to illustrate exemplary aspects providing cache subdivisions 200(0)-200(L), 200(0)-200(Y), 200(0)- 200(Z), 200(0)-200(X) comprising the cache lines 106(0)- 106(L), the sets 104(0)- 104(Y) of the cache lines 106(0)-106(L), the ways 108(0)-108(Z) of the cache lines 106(0)-106(L), and the banks 102(0)- 102(X) of the cache lines 106(0)- 106(L), respectively. In Figure 2A, the cache subdivisions 200(0)-200(L) each correspond to one of the cache lines 106(0)- 106(L), with the cache lines 106(0), 106(2), and 106(L) associated with QoS class 112(0) and the cache lines 106(1), 106(3) associated with QoS class 112(1). Each of the cache subdivisions 200(0)-200(L) is also associated with a corresponding QoSID tracking tag 202(0)-202(L), comprising a single bit. The QoSID tracking tags 202(0)-202(L) indicate that the cache line 106(1) is currently in use by the associated QoS class 112(1), while the cache lines 106(2) and 106(L) are currently in use by the associated QoS class 112(0). Likewise, the QoSID tracking tag 202(0) indicates that the cache line 106(0) is not presently in use by the associated QoS class 112(0), and the QoSID tracking tag 202(3) indicates that the cache line 106(3) is not presently in use by the associated QoS class 112(1).

[0043] In the example of Figure 2B, the cache subdivisions 200(0)-200(Y) each correspond to one of the sets 104(0)-104(Y) of the cache lines 106(0)-106(L). The sets 104(0), 104(2), and 104(Y) are associated with QoS class 112(0), while the sets 104(1), 104(3) are associated with QoS class 112(1). The QoSID tracking tags 202(0)-202(Y) associated with the cache subdivisions 200(0)-200(Y) indicate that the set 104(1) is currently in use by the associated QoS class 112(1), while the sets 104(2) and 104(Y) are currently in use by the associated QoS class 112(0). Similarly, the QoSID tracking tag 202(0) indicates that the set 104(0) is not presently in use by the associated QoS class 112(0), and the QoSID tracking tag 202(3) indicates that the set 104(3) is not presently in use by the associated QoS class 112(1).

[0044] In Figure 2C, the cache subdivisions 200(0)-200(Z) each correspond to one of the ways 108(0)-108(Z) of the cache lines 106(0)- 106(L). The ways 108(0), 108(2), and 108(Z) are associated with QoS class 112(0), while the ways 108(1), 108(3) are associated with QoS class 112(1). The QoSID tracking tags 202(0)-202(Z) associated with the cache subdivisions 200(0)-200(Z) indicate that the way 108(1) is currently in use by the associated QoS class 112(1), while the ways 108(2) and 108(Z) are currently in use by the associated QoS class 112(0). Likewise, the QoSID tracking tag 202(0) indicates that the way 108(0) is not presently in use by the associated QoS class 112(0), and the QoSID tracking tag 202(3) indicates that the way 108(3) is not presently in use by the associated QoS class 112(1).

[0045] Referring now to Figure 2D, the cache subdivisions 200(0)-200(X) in this example each correspond to one of the banks 102(0)-102(X) of the cache lines 106(0)- 106(L). The banks 102(0), 102(2), and 102(X) are associated with QoS class 112(0), while the banks 102(1), 102(3) are associated with QoS class 112(1). In this example, the QoSID tracking tags 202(0)-202(X) associated with the cache subdivisions 200(0)-200(X) indicate that the bank 102(1) is currently in use by the associated QoS class 112(1), while the banks 102(2) and 102(X) are currently in use by the associated QoS class 112(0). Similarly, the QoSID tracking tag 202(0) indicates that the bank 102(0) is not presently in use by the associated QoS class 112(0), and the QoSID tracking tag 202(3) indicates that the bank 102(3) is not presently in use by the associated QoS class 112(1).

[0046] To illustrate exemplary operations of the shared cache memory system 100 of Figure 1 for generating the approximate usage measurements 120, Figures 3A-3B are provided. In describing Figures 3A-3B, elements of Figures 1 and 2A-2D are referenced for the sake of clarity. In Figure 3 A, operations begin with the cache usage monitor 118 of Figure 1 associating each cache subdivision 200(0) of the plurality of cache subdivisions (e.g., cache subdivisions 200(0)-200(L), 200(0)-200(Y), 200(0)-200(Z), 200(0)-200(X)) of the shared cache memory system 100 with a QoS class 112(0) of a plurality of QoS classes 112(0)-112(N) (block 300). In this regard, the cache usage monitor 118 may be referred to herein as "a means for associating each cache subdivision of a plurality of cache subdivisions of the shared cache memory system with a QoS class of a plurality of QoS classes."

[0047] The cache usage monitor 118 next receives a memory access request 124 comprising a QoSID 126 (block 302). Accordingly, the cache usage monitor 118 may be referred to herein as "a means for receiving a memory access request comprising a QoSID." The cache usage monitor 118 accesses a cache subdivision 200(0) corresponding to the memory access request 124 among the plurality of cache subdivisions 200(0)-200(L), 200(0)- 200(Y), 200(0)-200(Z), 200(0)-200(X) (block 304). The cache usage monitor 118 may thus be referred to herein as "a means for accessing a cache subdivision corresponding to the memory access request among the plurality of cache subdivisions."

[0048] With continued reference to Figure 3 A, the cache usage monitor 118 determines whether the QoSID 126 of the memory access request 124 corresponds to the QoS class 112(0) associated with the cache subdivision 200(0) (block 306). In this regard, the cache usage monitor 118 may be referred to herein as "a means for determining whether the QoSID of the memory access request corresponds to the QoS class plurality of QoS classes associated with the cache subdivision." Based on the determining, the cache usage monitor 118 updates the QoSID tracking tag 202(0) associated with the cache subdivision 200(0) corresponding to the memory access request 124 based on the determining (block 308). Accordingly, the cache usage monitor 118 may be referred to herein as "a means for updating a QoSID tracking tag of a plurality of QoSID tracking tags associated with the cache subdivision corresponding to the memory access request based on the means for determining." Processing then resumes at block 310 of Figure 3B.

[0049] Turning now to Figure 3B, the cache usage monitor 118 generates an approximate usage measurement 120 for a QoS class 112(0) of the plurality of QoS classes 112(0)-112(Z) based on the plurality of QoSID tracking tags 202(0)-202(N) (block 310). The cache usage monitor 118 may thus be referred to herein as "a means for generating an approximate usage measurement for the QoS class of the plurality of QoS classes based on the plurality of QoSID tracking tags." In some aspects, operations of block 310 for generating the approximate usage measurement 120 may include the cache usage monitor 118 first determining a fraction of the plurality of cache subdivisions 200(0)-200(X) associated with the QoS class 112(0) (block 312). In this regard, the cache usage monitor 118 may be referred to herein as "a means for determining a fraction of the plurality of cache subdivisions associated with the QoS class." The cache usage monitor 118 may next determine a count of the plurality of cache subdivisions 200(0)-200(X) associated with the QoS class 112(0) for which an associated QoSID tracking tag 202(0) is set (block 314). Accordingly, the cache usage monitor 118 may be referred to herein as "a means for determining a count of the plurality of cache subdivisions associated with the QoS class for which the associated QoSID tracking tag is set." The cache usage monitor 118 may then divide the count of the cache subdivisions 200(0)-200(X) by the fraction to generate the approximate usage measurement 120 (block 316). The cache usage monitor 118 may thus be referred to herein as "a means for dividing the count of the plurality of cache subdivisions by the fraction to generate the approximate usage measurement."

[0050] Generating approximate usage measurements for shared cache memory systems may be provided in or integrated into any processor-based device. Examples, without limitation, include a set top box, an entertainment unit, a navigation device, a communications device, a fixed location data unit, a mobile location data unit, a mobile phone, a cellular phone, a computer, a portable computer, a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, and a portable digital video player. [0051] In this regard, Figure 4 is a block diagram of an exemplary processor-based system 400 that can include the shared cache memory system (SCMS) 100 having the cache controller 110 of Figure 1. In this example, the processor-based system 400 includes one or more CPUs 402, each including one or more processors 404. The CPU(s) 402 may be a master device. The CPU(s) 402 may have cache memory 406 coupled to the processor(s) 404 for rapid access to temporarily stored data. In some aspects, the cache memory 406 may comprise the shared cache memory system 100 and/or the cache controller 110 of Figure 1. The CPU(s) 402 is coupled to a system bus 408 and can intercouple master and slave devices included in the processor-based system 400. As is well known, the CPU(s) 402 communicates with these other devices by exchanging address, control, and data information over the system bus 408. For example, the CPU(s) 402 can communicate bus transaction requests to a memory controller 410 as an example of a slave device.

[0052] Other master and slave devices can be connected to the system bus 408. As illustrated in Figure 4, these devices can include a memory system 412, one or more input devices 414, one or more output devices 416, one or more network interface devices 418, and one or more display controllers 420, as examples. The input device(s) 414 can include any type of input device, including but not limited to input keys, switches, voice processors, etc. The output device(s) 416 can include any type of output device, including but not limited to audio, video, other visual indicators, etc. The network interface device(s) 418 can be any devices configured to allow exchange of data to and from a network 422. The network 422 can be any type of network, including but not limited to a wired or wireless network, a private or public network, a local area network (LAN), a wireless local area network (WLAN), a wide area network (WAN), a BLUETOOTH™ network, and the Internet. The network interface device(s) 418 can be configured to support any type of communications protocol desired. The memory system 412 can include one or more memory units 424(0)- 424(N).

[0053] The CPU(s) 402 may also be configured to access the display controller(s) 420 over the system bus 408 to control information sent to one or more displays 426. The display controller(s) 420 sends information to the display(s) 426 to be displayed via one or more video processors 428, which process the information to be displayed into a format suitable for the display(s) 426. The display(s) 426 can include any type of display, including but not limited to a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, etc. [0054] Those of skill in the art will further appreciate that the various illustrative logical blocks, modules, circuits, and algorithms described in connection with the aspects disclosed herein may be implemented as electronic hardware. The devices described herein may be employed in any circuit, hardware component, integrated circuit (IC), or IC chip, as examples. Memory disclosed herein may be any type and size of memory and may be configured to store any type of information desired. To clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. How such functionality is implemented depends upon the particular application, design choices, and/or design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.

[0055] The various illustrative logical blocks, modules, and circuits described in connection with the aspects disclosed herein may be implemented or performed with a processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.

[0056] It is also noted that the operational steps described in any of the exemplary aspects herein are described to provide examples and discussion. The operations described may be performed in numerous different sequences other than the illustrated sequences. Furthermore, operations described in a single operational step may actually be performed in a number of different steps. Additionally, one or more operational steps discussed in the exemplary aspects may be combined. It is to be understood that the operational steps illustrated in the flow chart diagrams may be subject to numerous different modifications as will be readily apparent to one of skill in the art. Those of skill in the art will also understand that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0057] The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.