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Title:
GENERATING A LOGIC DESIGN
Document Type and Number:
WIPO Patent Application WO2003021497
Kind Code:
A3
Abstract:
A technique to generate a logic design for use in designing an integrated circuit (IC). The technique includes embedding a combinatorial one-dimensional logic block within a two-dimensional schematic presentation to form a unified database. The technique also includes following a set of design capture rules, importing the combinatorial one-dimensional logic block, and notifying a designer when importing the combinatorial data block violates the set of design capture rules.

Inventors:
WHEELER WILLIAM
ADILETTA MATTHEW
Application Number:
PCT/US2002/027010
Publication Date:
February 05, 2004
Filing Date:
August 23, 2002
Export Citation:
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Assignee:
INTEL CORP (US)
International Classes:
G06F17/50; (IPC1-7): G06F17/50
Domestic Patent References:
WO1998037475A21998-08-27
Foreign References:
EP0433066A21991-06-19
EP1065611A22001-01-03
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