DESCRIPTION

GLITCH MONITOR AND CIRCUIT

The invention relates to a method and apparatus for monitoring glitches.

Glitches are short, undesired fluctuations of the value of an electrical or logical signal. Usually, a glitch is a fluctuation in the value of the voltage at a circuit node. It represents a temporary change in the signal level, typically for a period much shorter than the period of the signal.

A signal will be considered to be a glitch if its amplitude is at least half the value of the dynamic range of the signal. Smaller signal variations can be considered to be simply noise. This assumption is based on the fact that fluctuations of half the value of the dynamic range or more can propagate through combinatorial logic, whereas small variations do not. Accordingly, the effect of a glitch can be much worse than simple noise.

Glitches typically affect digital circuits. They have a number of causes, including race conditions in combinatorial logic, cross-talk and supply voltage noise, amongst others. Glitches have two main negative effects. Firstly, they can cause logical malfunction of the ciruit. The time for a voltage on a node to reach the desired state may be too large, and therefore latching elements of the circuit may sample incorrect states.

Secondly, the dissipated power in the circuit may increase due to undesired charging and discharging of capacitances.

Unfortuately, the presence of glitches is not completely avoidable in circuits, especially CMOS combinatorial circuits that do not have any special design effort to ensure that input signals do not switch simultaneously.

As integrated circuits get ever smaller, including in particular deep submicron technology, the prevalence of glitches increases.

One cause is that the variability of the devices formed in deep submicron technology is constantly increased. Neighbouring cells present

different electrical characteristics so even gates next to one another on a chip may have a larger process spread, and hence delay spread. This spread can generate glitches in cascaded combinatorial cells.

Secondly, the reduction in the supply voltage required for deep submicron technology and reduced power consumption reduces the signal voltage range and hence reduces noise margins.

For these reasons, problems caused by glitches are increasing.

A circuit to monitor glitches in a high speed data communications link has been proposed in US 6944804. The circuit has a de-glitch filter and compares the signal passed through the de-glitch filter with the unfiltered signal, and counts occasions when there is a significant difference.

According to an aspect of the invention, there is provided a glitch monitor according to claim 1. Unlike the glitch monitor of US6944804, the circuit includes one or more counters with up and down inputs connected to test paths having different characteristic frequencies. This allows the number of glitch events to be more reliably obtained, since there is no requirement to ensure an exact timing match between the different test paths. The glitch monitor may include a second input for connecting to a reference voltage, and the test paths may include differential amplifiers, each having a pair of differential inputs connected to the first and second inputs respectively. In this way, the glitch monitor can be arranged to operate with arbitrary voltage circuits. Each of the low pass filters may include a capacitor connected between the output of the respective amplifier and a constant voltage, the capacitors in different test paths having different values to have different characteristic frequencies. This provides a simple implementation.

In another aspect, there is provided a circuit with a glitch monitor as set out above connected to a circuit under test.

The glitch monitor may feed back counts of glitches to the circuit under test to control at least one operating condition in the circuit under test on the basis of the counted number of glitches.

For a better understanding of the invention, embodiments will now be described, purely by way of example, with reference to the accompanying drawings, in which:

Figure 1 is a circuit diagram of a first embodiment of the invention; and Figure 2 is a circuit diagram of an alternative embodiment of the invention.

The figures are schematic and not to scale.

Referring to Figure 1 , a device under test 10 has a circuit node 12 which in the embodiment is the output of a two-input NAND 14. The two inputs of the two-input NAND may be generated elsewhere in the circuit and propagate along different paths that should theoretically have the same delay. The device under test 10 also has a reference voltage generation circuit 16. In this embodiment, the reference voltage generation circuit 16 is capable of generating a constant voltage having a noise level that is negligible compared to the noise present at the circuit node 12. The reference voltage circuit 16 is connected to reference output node 18. In the example, the device under test operates on a voltage V _DDI and the reference voltage is half this voltage, VDDI/2.

The device under test 10 may be a dedicated circuit specially created for monitoring purposes or alternatively simply a part of the digital circuit. Thus, the circuit node 12 can be any node on the chip and hence the signal tested can be any digital signal available on the chip. The device under test operates at a known frequency, or up to a known frequency, which will be referred to as the predetermined frequency below. The device under test 10 is connected to glitch monitor 20. The glitch monitor 20 has two inputs, a signal input 22 which in the embodiment is shown connected to circuit node 12 and a reference input 24 shown connected to

reference output node 18. The glitch monitor operates on a voltage V _DD2 which need not be the same as the voltage V _DDI of the device under test 10. This enhances the flexibility of the glitch monitor 20.

The glitch monitor includes three test paths arranged in parallel, namely a first test path 26, a second test path 28 and a third test path 30. Each test path 26,28,30 includes a respective differential amplifier 32,34,36 at its input, a capacitor 38,40,42 and a buffer 44,46,48 at its output. Each differential amplifier has one of its inverting and non-inverting inputs connected to the signal input 22 and the other to the reference input 24. Thus, the first test path 26 includes a first differential amplifier 32 having an output connected to a first capacitor 38 and to the input of a first buffer 44. The second test path 28 includes a second differential amplifier 34 having an output connected to a second capacitor 40 and to the input of a second buffer 46. The third test path 30 includes a third differential amplifier 36 having an output connected to a third capacitor 42 and to the input of a third buffer 48. Each of the capacitors 38,40,42 has the other end connected to ground 50.

The capacitors 38,40,42 in combination with the output impedance of the respective differential amplifiers, constitute low-pass filters shorting higher frequencies than a characteristic frequency to ground. In alternative embodiments, alternative low pass filters may be used.

The differential amplifiers 32,34,36 themselves are selected to pass high frequencies, an order of magnitude above the characteristic frequencies.

The test paths 26, 28, 30 differ in that the capacitance values of the first second and third capacitors 38,40,42 vary. The capacitance value of the first capacitor 38 in the first test path may be chosen so that the respective characteristic frequency is in the range from the predetermined frequency to double the predetermined frequency. Accordingly, the first test path passes the signals on circuit node 12 at the predetermined frequency, but filters out significantly higher frequencies. The capacitance values of the capacitors in the other test paths are chosen to be lower so that the characteristic frequencies are significantly higher, to allow the transmission of high frequency glitches. The capacitances

and hence the characteristic frequencies in the second and third test paths are different, to allow different transmission of glitches in each path.

Purely by way of example, a low pass filter in the second test path may have a frequency in the range of 5 times to 10 times the predetermined frequency; and a low pass filter in the third test path has a frequency in the range 10 times to 20 times the predetermined frequency.

The outputs of the buffers of the test paths are connected to a first counter 52 and a second counter 54. Each of the first and second counters has an up input 56 and a down input 58. The down inputs of both counters are connected to the first path 26, i.e. to the output of the first buffer 44. The up input of the first counter 52 is connected to the second path 28, in particular to the output of the second buffer 46, and the up input of the second counter 54 is connected to the third path 30, in particular to the output of the third buffer 48. In this way, the first counter counts events that propagate through the second path but not the first, and the second counter counts events that propagate through the third path but not the first. Since signal transmissions propagate through all three test paths, the outputs of the first and second counters are, ideally, the number of transitions caused by glitches, which will be filtered out in the first path.

The use of different capacitance values in the second and third paths allows more detailed information on the nature of the glitches.

The present invention does not filter to remove glitches at the node 12 but instead indicates the glitch probablity in the system, which allows a suitable set of operating conditions to be chosen. The approach allows in general terms to minimise glitches in general, and is very compatible with modern digital signal design, dynamic voltage scaling and active body biasing. By adjusting parameters of the circuit under test 10, the glitch frequency can be reduced. Accordingly, the circuit can be used simply as a monitor to characterise the circuit under test and use the information for redesign. The circuit can also be used to test the accuracy of the simulation model.

In an alternative embodiment, instead of the second and third paths having different capacitance values, the second and third paths have different threshold voltages at the inputs of the differential amplifiers.

A further variation is to omit the capacitor completely from one of the second and third paths.

Further, note that although the embodiment described has three test paths, a simpler design simply uses a pair of test paths and a single counter, omitting the third test path 30 and second counter 54.

A further variation is to omit the reference voltage input 24 from the glitch monitor if the reference voltage is known. This may be the case when operating from a circuit of known constant voltage. In this case, the inputs to the differential amplifiers 32,34,36 may be generated in the glitch monitor 20 or alternatively the differential amplifiers 32,34,36 may optionally be replaced by buffers or other amplifiers. It will be noted that the characteristic frequency of each test path in the above embodiments is not simply a parameter of the capacitor, but also of the output impedance of the differential amplifier. A resistor and/or an inductor may optionally be added in each test path between the differential amplifier and buffer to cooperate with the capacitor to define the characteristic frequency. This can provide a better defined characteristic frequency. Alternative low pass filter arrangements may also be adopted. The function of the buffers 44,46,48 is to electrically isolate the low pass filters from each other and to increase the slope of the signals so that the counters can detect the rising edge with greater precision. Alternatively, the buffers can be omitted if the counters are sufficiently reliable without them.

In alternative arrangements, the reference voltage input on reference voltage inputs 24 is not directly connected to the inputs of the differential amplifiers 32,34,36. For example, the reference voltage on reference input 24 may simply be V _DDI and a circuit in glitch monitor 20 may provide a voltage of half this amount, V _DDI /2, to the inverting inputs of the differential amplifers 32,34,36 in the test paths.

Also, the voltage input 22 need not be directly connected to the differential amplifiers 32,34,36 but other components may be included if required. For example, some form of overload protection may be introduced on voltage input 22. In a second embodiment, shown in Figure 2, the glitch monitor 20 is used as a monitor in a feedback loop operating to control the operating conditions of the circuit under test 10. The glitch monitor 20 includes output circuit 60 which is driven by the outputs of counters 52, 54 to generate a feedback signal to control operating condition circuit 62 in the circuit under test. For example, the operating condition circuit may control the supply voltage value, the clock speed, or other parameters.

The output circuit 60 and operating condition control circuit 62 may carry out the control on the basis of the quality of the chip making up the circuit under test 10, the computational load, the temperature, and the supply voltage value, using one or more sensors 64 as well as the glitch monitor 20. For example, one sensor 66 may be used to monitor the temperature of the circuit under test, and another sensor 68 may monitor power consumption.

The feedback and control functionality may be provided in the output circuit 60, the operating condition control circuit 62, or both, as appropriate in any particular case.

In this way, the circuit under 10 can be controlled in real time, in use, to minimise the probability of logical errors and reduce excess power consumption caused by glitches.

The glitch monitor 20 aims to assist in the robustness of circuit design. Worst case corner design is becoming unfeasible for many applications and so many products will need to have a local control circuit to optimise performance.