Global positioning system receivers for consumer use have dramatically decreased in size and price due to on-going developments in semi-conductor fabricating technology and the manufacturing scales of economy possible for consumer products. Recently, affordable single unit GPS receivers have been created which are the size of about a credit card. These receivers may be used with a lap top computer in order to determine a present location.

The small GPS receivers for use with computers are typically fabricated on a printed circuit board. In this respect, the receiver circuitry is placed on one side of the board, while the antenna for the GPS system is placed on the opposite side. However, a problem develops inasmuch as the receiver circuitry may generate noise and interference with the GPS antenna.

Specifically, the high frequency operation of the GPS receiver circuitry creates noise which may be received by the GPS antenna disposed on the opposite side of the PCB.

Prior art methods of reducing noise from the GPS receiver circuitry on integrated systems include shielding the circuitry within a metal enclosure. The metal enclosure is connected to ground such that any stray noise created by the GPS receiver circuitry will be

attenuated. However, this is not desirable because it increases the size and cost of manufacturing the GPS system. The shielding must be sized to adequately attenuate the noise created by the GPS receiver circuitry.

The present invention addresses the above-mentioned deficiencies in prior art integrated GPS systems inasmuch as the present invention reduces noise between the GPS receiver circuitry and the GPS antenna by mitigating the use of metal shielding. In this respect, the present invention provides for a integrated GPS receiver which is compact in size and reduces the need for metal shielding.

BRIEF SUMMARY OF THE INVENTION An integrated GPS receiver system is disclosed. The GPS receiver system comprises a printed circuit board having a first side and a second side. Mounted to the first side of the printed circuit board is a GPS antenna. Similarly, mounted to the second side of the printed circuit board is a GPS receiver. The integrated GPS receiver system further includes a plurality of shielding vias extending through the printed circuit board from the first side to the second side. The vias are operative to reduce noise from the GPS receiver circuit to the GPS antenna.

In the preferred embodiment of the present invention, the shielding vias are disposed about the periphery of printed circuit board. In this respect, the vias will surround the traces of the printed circuit board. In particular, the vias may surround noisy sections (i. e., noisy traces) of the printed circuit board. The vias have a generally rectangular cross sectional area and are spaced about 0.1 inches around the periphery.

In the preferred embodiment of the present invention, the printed circuit board will comprise a ground plane layer disposed between the first and second sides thereof. The shielding vias will be in electrical communication with the ground plane layer in order to reduce noise from the GPS receiver circuit. Furthermore, it is contemplated that the printed circuit board of the GPS receiver system will further include a second ground plane layer which is disposed between the GPS antenna and the first side of the printed circuit board.

The vias will be in electrical communication with the second ground plane layer in order to

further prevent noise between the GPS receiver circuit and the GPS antenna.

As previously mentioned, each of the shielding vias extend through the printed circuit board. In this respect, each of the vias will comprise metallic plating throughout the depth of the printed circuit board. Additionally, the vias may be positioned around the traces of a routing layer which is disposed between the first and second sides of the printed circuit board. In accordance with the present invention, the vias reduce noise between the GPS receiver circuit and the GPS antenna by about 5db.

In accordance with the present invention, there is provided a method of reducing noise between a GPS antenna and a GPS receiver circuit of an integrated GPS receiver system. The method comprises attaching the GPS antenna to the first side of the printed circuit board. Next, the GPS receiver is attached to a second side of the printed circuit board.

Finally, a plurality of shielding vias are formed within the printed circuit board. Each of the vias is formed to extend from the first side of the printed circuit board to the second side such that the vias will surround the traces of the printed circuit board in order to reduce noise therefrom.

BRIEF DESCRIPTION OF THE DRAWINGS These as well as other features of the present invention will become more apparent upon reference to the drawings wherein: Figure 1 is a cross-sectional view of an integrated GPS receiver system constructed in accordance with the present invention; Figure 2 is a plan-view of a top layer of a printed circuit board used in conjunction with the invention shown in Figure 1 ; Figure 3 is a plan-view of a grounding plane layer of the printed circuit board shown in Figure 1; Figure 4 is a plan-view of a routing layer of the printed circuit board shown in Figure 1; and Figure 5 is a plan-view of a bottom layer for the circuit board shown in Figure 1.

DETAILED DESCRIPTION OF THE INVENTION Referring now to the drawings wherein the showings are for purposes of illustrating a preferred embodiment of the present invention only, and not for purposes of limiting the same. Figure 1 is a cross-sectional view of an integrated GPS receiver system 10 constructed in accordance with the present invention. The integrated GPS receiver system 10 comprises a multi-layer printed circuit board (PCB) 12 formed from a top board 24, a middle board 26 and a bottom board 28. In this respect, the middle board 26 is disposed between the top board 24 and the bottom board 28. The PCB 12 has a top or first side 22 and a bottom or second side 30 disposed opposite thereof, as seen in Figure 1. In laminar juxtaposition on the first side 22 (of the top board 24) is a top layer 14. The top layer 14 includes traces 48, as seen in Figure 2. The traces 48 are metallic traces formed in the printed circuit board manufacturing process. Similarly, disposed between the top board 24 and the middle board 26 is a grounding plane layer 16. The grounding plane layer 16 also includes traces 48, as seen in Figure 3. The printed circuit board 12 further includes a routing layer 18 disposed between the middle board 26 and the bottom board 28. Referring to Figure 4, the routing layer 18 also includes traces 48. Finally, the PCB 12 includes a bottom layer 20 disposed in laminar juxtaposition with the second side 30 (of bottom board 28), as seen in Figure 1.

Referring to Figure 1, the integrated GPS receiver system 10 furtherincludes a GPS receiver circuit 32 disposed on and attached to top layer 14 (i. e., first side 22) of multilayer PCB 12. Specifically, GPS receiver circuit 32 comprises integrated circuits such as digital signal processing chips and receiver chips which receive and decode GPS signals in order to determine the location of the GPS receiver system 10. Each of the integrated circuits is soldered to respective metallic contacts of top layer 14.

Attached to the bottom layer 20 (i. e., second side 30) is an insulating solder mask 34.

In laminar juxtaposition with insulating solder mask 34 is a conductive adhesive sheet 36.

The conductive adhesive sheet 36 is used to bond a metallic ground plane 38 to the multilayer PCB 12. The ground plane 38 is used with a GPS patch antenna 40. Specifically, the GPS antenna 40 is attached to the ground plane 38, as seen in Figure 1. The GPS antenna 40 is operative to receive GPS location signals from orbiting satellites. In this respect, the

integrated GPS receiver system 10 is fully operative to receive and decode GPS signals, as is currently known in the art. Typically, the integrated GPS receiver system 10 will be used with a portable personal computer for determining location. In this respect, the integrated GPS receiver system 10 is a peripheral device which may be added or integrated into a portable personal computer.

In accordance with the preferred embodiment of the present invention, the integrated GPS receiver system 10 further includes a plurality of shielding vias 42 disposed within multilayer PCB 12. Each of the vias 42 extends from the first side 24 to the second side 30 of the PCB 12 and is formed from a metallic material (i. e., copper) which flows through the top, middle and bottom boards 24,26,28 during manufacturing of the multilayer PCB 12.

Specifically, a respective hole or aperture is formed within each top, middle or bottom board 24, 26,28 in the location of a desired via 42. The hole or aperture may be formed within each board 24,26, and 28 either prior to bonding each board 24,26, and 28 to one another, or after bonding thereof. After bonding top, middle, and bottom boards 24,26, and 28, then copper is plated through each hole or aperture in order to form a respective shielding via 42.

In this respect, each of the vias 42 is continuous throughout each of the layers 14,16,18, and 20, as well as boards 24,26, and 28 of the multilayer PCB 12. As seen in Figure 1, the shielding vias 42 will be in electrical communication with the conductive adhesive sheet 36 and the ground plane 3 8 through holes in the insulating solder mask 34. Additionally, each of the vias 42 is in electrical communication with ground plane layer 16 disposed between first board 24 and middle board 26.

The vias 42 function as electromagnetic shielding for the GPS receiver circuit 32.

Specifically, the GPS receiver circuit 32 creates noise which may interfere with the GPS patch antenna 40. This is undesirable and can lead to inaccurate reception of signals from the GPS satellite system. As previously mentioned above, typically the GPS receiver circuit 32 will be enclosed within a metal enclosure in order to reduce the noise created thereby.

However, in accordance with the present invention, the vias 42 are operative to reduce the noise created by the GPS receiver circuit 32 by as much as 5db. Because each of the vias 42 is in electrical communication with ground plane layer 16 through to the metal antenna

ground plain 38, the vias 42 are operative to receive and mitigate noise and interference created by GPS receiver circuit 32.

Referring now to Figures 2 to 5, the vias 42 are positioned around the periphery of the multilayer PCB 12 and the noisy traces of the GPS receiver circuit 32. Specifically, as seen in Figure 5, vias 42 are disposed adjacent to the continuous edge 44 of the PCB 12.

Additionally, a series of interior shielding vias 50 surround portions of the GPS receiver circuit 32 which produce considerable noise. The interior vias 50 are similar to the exterior vias 42 inasmuch as they both extend continuously through the PCB 12 from the first side 22 to the second side 30. Each of the vias 42 and 50 have a generally rectangular cross- sectional area, as seen in Figure 2,3, and 4 with a spacing of about 0.1 inches. Ideally, the vias are equally spaced along the edge 44 of PCB 12 to mitigate noise from GPS receiver circuit 32.

The placement and number of shielding vias 42 and 50 mitigate the noise from the GPS receiver circuit 32. In this respect, shielding enclosures may be reduced and/, or. totally removed from the integrated GPS receiver system 10. It will be recognized that the fabrication of the vias 42 is inexpensive and a component of the conventional manufacturing process of the PCB 12. Accordingly, the present invention provides an economical method for reducing noise from the GPS receiver circuit 32.

Additional modifications and improvement of the present invention may also be apparent to those of ordinary skill in the art such as varying the placement and size of the shielding vias 42 and 50. Thus, the particular combination of parts described and illustrated herein is intended to represent only a certain embodiment of the present invention, andis not intended to serve as a limitation of alternative devices within the spirit and scope of the invention.