BACKGROUND

In the fields of wireless communication and power management, various components can be implemented using solid-state devices. For example, in radio frequency (RF) communication, the RF front-end is a generic term for the circuitry between an antenna and a digital baseband system. Such RF front-end components may include one or more resonators. Due, in part, to robust electromechanical properties, including high acoustic velocities and low elastic losses along with strong piezoelectric coupling, a III-N material can be advantageous for RF resonator applications. III-N based resonators are often one of the key components of RF filter technologies.

BRIEF DESCRIPTION OF THE DRAWINGS

The material described herein is illustrated by way of example and not by way of limitation in the accompanying figures. For simplicity and clarity of illustration, elements illustrated in the figures are not necessarily drawn to scale. For example, the dimensions of some elements may be exaggerated relative to other elements for clarity. Also, various physical features may be represented in their simplified“ideal” forms and geometries for clarity of discussion, but it is nevertheless to be understood that practical implementations may only approximate the illustrated ideals. For example, smooth surfaces and square intersections may be drawn in disregard of finite roughness, comer-rounding, and imperfect angular intersections characteristic of structures formed by nanofabrication techniques. Further, where considered appropriate, reference labels have been repeated among the figures to indicate corresponding or analogous elements.

Figure 1 A illustrates a cross-sectional view of a resonator including a III-N material, in accordance with an embodiment of the present disclosure.

Figure 1B illustrates a plan view of the resonator structure of Figure 1 A.

Figure 1C illustrates a cross-sectional view of a resonator including a III-N material, in accordance with an embodiment of the present disclosure.

Figure 1D illustrates a plan view of a resonator including a III-N material, in accordance with an embodiment of the present disclosure.

Figure 1E illustrates a plan view of a resonator including a III-N material, in accordance with an embodiment of the present disclosure.

Figure 2A illustrates a cross-sectional view of a resonator including a III-N material between an oxide barrier, in accordance with an embodiment of the present disclosure.

Figure 2B illustrates a plan view of the resonator structure of Figure 2A.

Figure 3 illustrates a method for fabricating a resonator such as the resonator, in accordance with an embodiment of the present disclosure.

Figure 4A illustrates a cross-sectional view of an electrode formed in a substrate, in accordance with an embodiment of the present disclosure.

Figure 4B illustrates a cross-sectional view of the structure of Figure 4A following the formation of a layer of a III-N material formed above a substrate and a layer of hardmask material formed above the layer of the III-N material, in accordance with embodiments of the present disclosure.

Figure 4C illustrates a cross-sectional view of the structure of Figure 4B following the formation of one or more openings in the layer of the III-N material.

Figure 4D illustrates a cross-sectional view of the structure of Figure 4C following the formation of an alloy, the formation of a cavity in the substrate under the first layer, the formation of a liner on a surface of the substrate within the cavity, and the formation of a cantilevered structural member exposing the cavity.

Figure 4E illustrates a cross-sectional view of the structure of Figure 4D following the formation of a dielectric layer on the alloy in the cavity and outside the cavity.

Figure 4F illustrates a cross-sectional view of the structure of Figure 4E following the planarization of the dielectric layer and the alloy.

Figure 4G illustrates a cross-sectional view of the structure of Figure 4F following the formation of a second electrode on the layer of the PI-N material in the vicinity of the cavity.

Figure 4H illustrates a cross-sectional view of the structure of Figure 4G following the formation of a second dielectric layer on the alloy and the second electrode, in accordance with an embodiment of the present disclosure.

Figure 41 illustrates a plan-view of the structure of Figure 4H following the formation of a contact opening to couple with the first electrode, in accordance with an embodiment of the present disclosure.

Figure 4J illustrates a plan-view of the structure of Figure 41 following the formation of a contact to couple with the first electrode, in accordance with an embodiment of the present disclosure.

Figure 4K illustrates a cross-sectional view of the structure of Figure 4J following the patterning of the layer of the III-N material to outline a shape of a cantilever structure to be formed, in accordance with an embodiment of the present disclosure. Figure 4L illustrates a cross-sectional view of the structure of Figure 4K following the removal of the second and the first dielectric layers from above the cavity and the removal of the first dielectric layers from the cavity.

Figure 5 illustrates a cross-sectional view of a resonator structure adjacent to a III-N transistor above the substrate.

Figure 6 is a functional block diagram of a group III-N SoC implementation of a mobile computing platform, in accordance with an embodiment of the present disclosure.

Figure 7 illustrates a computing device in accordance with embodiments of the present disclosure.

Figure 8 illustrates an integrated circuit structure in accordance with embodiments of the present disclosure.

DESCRIPTION OF THE EMBODIMENTS

Devices including IP-N semiconductor materials for RF filter applications and their methods of fabrication are described. In the following description, numerous specific details are set forth, such as novel structural schemes and detailed fabrication methods in order to provide a thorough understanding of embodiments of the present disclosure. It will be apparent to one skilled in the art that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known features, such as operations associated with III-N resonators, are described in lesser detail in order to not unnecessarily obscure embodiments of the present disclosure. Furthermore, it is to be understood that the various embodiments shown in the Figures are illustrative representations and are not necessarily drawn to scale.

Certain terminology may also be used in the following description for the purpose of reference only, and thus are not intended to be limiting. For example, terms such as“upper”, “lower”,“above”, and“below” refer to directions in the drawings to which reference is made. Terms such as“front”,“back”,“rear”, and“side” describe the orientation and/or location of portions of the component within a consistent but arbitrary frame of reference which is made clear by reference to the text and the associated drawings describing the component under discussion. Such terminology may include the words specifically mentioned above, derivatives thereof, and words of similar import.

In the following description, numerous details are set forth. However, it will be apparent to one skilled in the art, that the present disclosure may be practiced without these specific details. In some instances, well-known methods and devices are shown in block diagram form, rather than in detail, to avoid obscuring the present disclosure. Reference throughout this specification to“an embodiment” or“one embodiment” or“some

embodiments” means that a particular feature, structure, function, or characteristic described in connection with the embodiment is included in at least one embodiment of the disclosure. Thus, the appearances of the phrase“in an embodiment” or“in one embodiment” or“some embodiments” in various places throughout this specification are not necessarily referring to the same embodiment of the disclosure. Furthermore, the particular features, structures, functions, or characteristics may be combined in any suitable manner in one or more embodiments. For example, a first embodiment may be combined with a second embodiment anywhere the particular features, structures, functions, or characteristics associated with the two embodiments are not mutually exclusive.

As used in the description and the appended claims, the singular forms“a”,“an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term“and/or” as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

The terms“coupled” and“connected,” along with their derivatives, may be used herein to describe functional or structural relationships between components. It should be understood that these terms are not intended as synonyms for each other. Rather, in particular embodiments,“connected” may be used to indicate that two or more elements are in direct physical, optical, or electrical contact with each other.“Coupled” may be used to indicated that two or more elements are in either direct or indirect (with other intervening elements between them) physical or electrical contact with each other, and/or that the two or more elements co-operate or interact with each other (e.g., as in a cause an effect

relationship).

The terms“over,”“under,”“between,” and“on” as used herein refer to a relative position of one component or material with respect to other components or materials where such physical relationships are noteworthy. For example, in the context of materials, one material or material disposed over or under another may be directly in contact or may have one or more intervening materials. Moreover, one material disposed between two materials may be directly in contact with the two layers or may have one or more intervening layers. In contrast, a first material“on” a second material is in direct contact with that second material/material. Similar distinctions are to be made in the context of component assemblies. As used throughout this description, and in the claims, a list of items joined by the term“at least one of’ or“one or more of’ can mean any combination of the listed terms. For example, the phrase“at least one of A, B or C” can mean A, B, C, A and B; A and C; B and C; or A, B and C.

In the fields of wireless communication and power management, various components can be implemented using solid-state devices. For example, in radio frequency (RF) communication, the RF front-end is a generic term for the circuitry between an antenna and a digital baseband system. Such RF front-end components may include one or more III-N material based resonators. To achieve resonator structures, the III-N material may be released from the substrate to form structures that allow for mechanical motion required for resonance. In some embodiments described further below, a release can be accomplished by depositing a group III material, such as Ga, on an exposed portion of a silicon substrate. A group Ill-silicon eutectic may result along with the formation of a cavity in the substrate. Extra processing operations associated with forming sacrificial structures that would otherwise facilitate a release can therefore be avoided. Depending on the desired performance, the resonator structure may include cantilevered structures that have various numbers of beams and/or beams of various shapes.

In some embodiments described further below, III-N based resonators extend over a cavity in a substrate that includes a group IV material. The structure may further include a liner on a surface of the substrate within the cavity, and this liner may include a group III material, the group IV material and nitrogen. A structural member of a resonator fashioned from a group III-N material may be cantilevered over this cavity. The liner may also be adjacent to a lowermost surface of the structural member. An electrode structure including a first electrode and a second electrode may be further coupled to the structural member. The first electrode and the second electrode may be proximal to an edge of the cavity for advantageous operation of the resonator.

Figure 1 A illustrates a cross-sectional view of a resonator 100 including a III-N material, in accordance with an embodiment of the present disclosure. In this exemplary embodiment, the resonator 100 includes a cavity 102 in a substrate 104. The substrate 104 advantageously includes a group IV material, such as silicon. The silicon substrate may have a (100) top surface. A silicon substrate with a (100) top surface may facilitate co-integration of a GaN transistor with the resonator 100. In another embodiment, a silicon substrate has a (111) top surface. A liner 106 has a liner portion 106A on a surface 104A of the substrate 104 that surrounds the cavity 102. The liner 106 includes a group III material, the group IV material that is also in the substrate 104, and nitrogen A structural member 108 including a III-N material is cantilevered over the cavity 102. As depicted in the cross-sectional illustration, the structural member 108 has a continuous portion over the substrate 104. The liner 106 also has a liner portion 106B and a liner portion 106C adjacent to a lowermost (bottom) surface 108A of the structural member 108. The liner 106 has thickness T _L , as illustrated. A gap 114 at a sidewall of the structural member 108 exposes the cavity 102. An electrode structure including an electrode 110 and an electrode 112 is coupled to the structural member 108. The electrode 110 may be in the substratel04, as illustrated, or on the substrate 104.

The electrode 110 and the electrode 112 are proximal to an edge of the cavity for

advantageous operation of the resonator 100. In an embodiment, the electrode 110 and the electrode 112 include a metal such as TiN, W, TaN, Ru.

In the illustrative embodiment, the cavity 102 has a shape where a cavity separation Sc between the surface 108 A of the structural member 108 and the substrate surface 104A varies along a cavity length LQ. For the cavity 102, the separation Sc has a maximum value at a center of the cavity 102, and a minimum value near a perimeter edge of the cavity 102. The maximum separation may be a function a thickness Ts, of the structural member 108, for example. In an embodiment, the separation, Sc, at the center of the cavity 102 is at least lpm. The cavity length Lc may be between lOpm and lOOpm, for example.

Figure 1B illustrates a plan view of the resonator 100, with the B-B’ of the cross- sectional illustration of Figure 1A further shown in dashed line. In the illustrative embodiment, the structural member 108 includes a beam 108B. The gap 114 separates a sidewall of the beam 108B from a sidewall of a remainder of the structural member 108. In some embodiments, the beam has a beam length L _B between 8pm and 90pm. In some such embodiments, the beam has a beam width W _B between 2pm and 4pm. A boundary of the cavity 102 is indicated by the dashed line 120. In the illustrative embodiment, the dashed line 120 defines a cavity having an elliptical shape. Other cavity shapes, such as circular or rectangular, are also possible as the cavity shape can depend on the methods employed to fabricate the cavity. A contact structure 116 for coupling the electrode 110 (indicated in dashed line) is also depicted in the plan view illustration of Figure IB. The electrode 110 has a portion that extends beyond the electrode 112 (in the negative Z-axis direction). The contact structure 116 is coupled with the portion of the electrode 110 that extends beyond the electrode 112, through the material of the structural member 108. In the illustrated embodiment, an isolation layer 118 surrounds the contact electrode 116. The isolation 118 may include any material that has sufficient dielectric strength to provide electrical isolation such as, but not to, limited silicon dioxide, silicon nitride, silicon oxynitride, carbon doped nitride and carbon doped oxide.

In an embodiment, the structural member 108 is a III-N material. The III-N material is advantageously monocrystalline. In some exemplary embodiments, the III-N material includes aluminum, such as an alloy of AIN. Although in some exemplary embodiments the AIN alloy is binary, tertiary or even quaternary alloys are also possible. For AIN

embodiments, the structural member 108 may have a thickness Ts that is between lpm and 2.5pm. The thickness Ts may be correlated with the cavity separation S _c at a center of the cavity. For example, when the thickness Ts is between lpm and 2.5pm the maximum cavity separation is between l .5pm and 3pm.

In an embodiment, the liner 106 includes a group III material that is monocrystalline. In one embodiment, the group III material includes Gallium. In some such embodiments where the substrate includes silicon, the liner is an alloy including gallium, silicon and nitrogen. Although the liner composition may vary, in some embodiments the gallium is between 20 atomic percent and 50 atomic percent. The composition of the alloy may not be uniform in all portions of the liner 106. In an embodiment, the liner has a thickness, TL, between lOnm and lOOnm. In other examples, the liner 106 has a non-uniform thickness along the surface 104A of the cavity and a non-uniform thickness along the lowermost structural member surface 108A. The thickness of the liner 106 may vary by up to 50% along the surfaces 104A and 108 A. Due to the geometry of the cavity 102, the liner portion 106C at an outer edge of the cavity 102 may have the greatest thickness.

In an embodiment, further illustrated in Figure 1C, a resonator 150 includes a second structural member layer 122 including the material of the liner 106 on the structural member 108. Depending on the resonator application and design constraints on the structural beam 108B, second structural member layer 122 has a thickness that may be greater than, equal to, or less than, the thickness of the liner 106. In an embodiment, the thickness of the second structural member layer 122 is between 50nm and 200nm. In contrast to the resonator structure of Figure 1A, the electrode 112 of resonator 150 is on the second structural member layer 122.

Figure 1D illustrates a plan view of a resonator 160, in accordance with an embodiment of the present disclosure. A cross-sectional illustration of the resonator 160 taken along the direction B-B’ is the same or substantially the same as the cross-sectional illustration of the resonator 100. In the illustrative embodiment, the structural member 108 includes a first structural beam 108C and a second structural beam 108D. The gap 114 separates a sidewall of the structural beam 108C and a sidewall of the structural beam 108D from a sidewall of the structural member 108. In an embodiment, each of the structural beams 108B and 108C have a beam length L _B between 8pm and 90pm. In an embodiment, each of the structural beams 108B and 108C have a beam width W _B between 2pm and 4pm. In other embodiments, (not illustrated) each of the structural beams 108C and 108D have a different length and width. An outline (indicated by the dashed line 120) defines a boundary of the cavity 102. In the illustrative embodiment, the boundary 120 defines a cavity having an elliptical shape. A contact structure 116 couples to the electrode 110, and the electrode 112 couples the structural member 108.

Figure 1E illustrates a plan view of a resonator 170, in accordance with an embodiment of the present disclosure. In the illustrative embodiment, the structural member 108 includes a serpentine shaped structural beam 108E that extends from one portion of the cavity 102 to an opposite end of the cavity 102. The gap 114 separates a sidewall of the serpentine-shaped structural beam 108E from a sidewall of the structural member 108. The serpentine-shaped structural beam 108E has a number of turns that can be utilized to tune the resonant frequency of the resonator 170. In the illustrative embodiment, the number of turns is 6. In other embodiments, the number of turns is between 5 and 20. In an embodiment, serpentine-shaped structural beam 108E has a beam width W _B between 2pm and 4pm. An outline (indicated by the dashed line 120) defines a boundary of the cavity 102. In the illustrative embodiment, the dashed line 120 defines a cavity with a circular shape. A contact structure 116 couples to the electrode 110 (dashed lines), and the top electrode 112 couples to the structural member 108.

Figure 2A illustrates a cross-sectional view of a resonator 200, in accordance with an embodiment of the present disclosure. In an embodiment, the resonator 200 includes a cavity 202 in the substrate 104, where the cavity 202 is surrounded by an isolation layer 204 embedded within the substrate 104. An edge portion of the cavity 202 exposes a sidewall 204B of the isolation 204. The shape of the cavity is concaved up and is substantially the shape of the cavity 202. The resonator 200 includes a liner 206. The liner 206 includes material that is the same, or substantially the same, as the material of the liner 106. In the illustrative embodiment, the liner 206 is has a liner portion 206A on surface 104A of the substrate 104 within the cavity 202, a liner portion 206B adjacent to sidewall 204A. The resonator 200 includes a structural member 208 cantilevered over the cavity 202 and a liner portion 206C adjacent to a lowermost structural member surface 208 A.

Figure 2B illustrates a plan view of the resonator 200, with the B-B’ line of the cross- sectional illustration of Figure 2A illustrated in dashed line. In the illustrative embodiment, the cavity 202 has a boundary 220 that is rectangular in shape as confined by the shape of the isolation 204. In other examples, while the shape of the isolation 204 can be rectangular, a cavity surrounded by isolation may also be elliptical or circular. In other embodiments, the boundary 220 can have a shape that is elliptical or circular. In an embodiment, the resonator 200 includes the structural beam 108B. In other embodiments, the resonator 200 may have a plurality of structural beams, such as those in the resonator structure 160 or have a serpentine shaped beam as in resonator 170. Gap 214, in resonator 200, separates an elongated portion of the beam 208B from the structural member 208. Resonator 200 further includes the first electrode 110 coupled with the structural member 208 and a second electrode 112 also coupled with the structural member 208. In an embodiment, the first electrode is adjacent to a sidewall of the isolation 204 that is opposite to the cavity 202. The first electrode 110 has a portion that extends (in the negative Z-axis direction) beyond the second electrode 112. Contact structure 116 is coupled with portion of the electrode 110 that extends beyond the electrode 112, through the material of the structural member 108. In an embodiment, the isolation layer 118 surrounds the contact electrode 116

Referring once again to Figure 2A, examples of the isolation 204 may include any material that has sufficient dielectric strength to provide electrical isolation such as, but not to, limited silicon dioxide, silicon nitride, silicon oxynitride, carbon doped nitride and carbon doped oxide. In an embodiment, the isolation has a height Hi between 500nm and 2um.

Figure 3 illustrates a method 301 for fabricating a resonator such as the resonator 100, in accordance with an embodiment of the present disclosure. Method 301 begins with receiving a substrate including a silicon for e.g., and forming an electrode in the substrate at operation 310. In a subsequent operation 320, a layer of III-N material is deposited on the substrate and patterned to expose a portion of the substrate. The method 301 is continued at operation 330 with the formation of an alloy including a group III element and silicon. The operation 330 includes forming a cavity in the substrate and a liner including the alloy in the cavity. The method 301 is continued in operation 340 with the deposition of an oxide in the cavity and on the alloy, and in operation 350 with the planarization of the oxide and the alloy above the layer of III-N material. In an embodiment, the method 301 is continued in operation 360 with the formation of a top electrode on the layer of III-N material. The method 301 is continued in operation 370 with the patterning of the layer of III-N material to form a beam structure and with removal of the oxide to form a cantilevered member above the cavity.

Figures 4A-4K illustrate various cross-sectional and plan views of a method to fabricate the resonator 100 depicted in Figure 1 A.

Figure 4A illustrates a cross-sectional view of the electrode 110 formed in the substrate 104, in accordance with an embodiment of the present disclosure. In an

embodiment, a trench is patterned into the substrate 104, and a metal layer is deposited into the trench. The metal layer may be planarized, resulting in the formation of the electrode 110 in the substrate 104. In the illustrative embodiment, the electrode has a thickness approximately between 50nm and lOOnm. The uppermost surface of the electrode may be coplanar, or substantially coplanar, with the surface of the substrate after the planarization process.

Figure 4B illustrates a cross-sectional view of the structure of Figure 4A following the formation of a layer of a III-N material 402 formed above the substrate 104 and on the electrode 110 and the formation of a hardmask layer 404 above the layer of the III-N material 402, in accordance with embodiments of the present disclosure. In an exemplary

embodiment, the III-N material 402 includes a layer of crystalline AIN and has a thickness Ts that is between lpm - 2.5pm. The hardmask layer is deposited to a thickness between 500nm and lpm to enable patterning of a thick A1N (greater than or equal to lpm). In an embodiment, the hardmask layer includes a silicon dioxide, silicon nitride, silicon oxynitride, carbon doped nitride and carbon doped oxide.

Figure 4C illustrates a cross-sectional view of the structure of Figure 4B following the formation of one or more openings in the layer of the III-N material 402. In an embodiment, a layer of resist is patterned over the hardmask layer 404 to form a resist mask. The resist mask is then utilized to etch the hardmask layer 404 to form an opening 406. The opening 406 may have a length and a width betweenl00nm-500nm. In other examples, there may be more than one openings formed. Multiple openings may be utilized to control the size and shape of a cavity to be formed in a subsequent operation.

In one example, the resist is removed after the hardmask layer 404 is patterned and the underlying III-N material 402 is etched using the patterned hardmask layer 404. The etch extends the opening 406 into the III-N material 402 and exposes the substrate 104. In one embodiment, the hardmask is then subsequently removed after the III-N material 402 is etched as illustrated in Figure 4C.

Figure 4D illustrates a cross-sectional view of the structure of Figure 4C following the formation of a cavity in the substrate under the first layer, formation of a cantilevered structural member above the cavity, and formation of an alloyed liner on a surface of the substrate within the cavity and on the cantilevered structure. In an embodiment, a trimethyl- gallium gas is flowed onto the exposed surface of the substrate in the presence of a nitrogen or ammonia gas at high temperatures. In one particular instance the processing temperature is above 900 degrees Celsius. The high temperature process may cause thermal

decomposition of trimethyl-gallium resulting in release of Ga atoms that subsequently react with the silicon in the substrate. A portion of the silicon in the substrate 104, exposed by the opening 406, is consumed during the deposition process and leads to the formation of a cavity 408. In one embodiment, the cavity 408 has a bowl-shaped profile as is depicted in Figure 4D creating a cantilevered III-N material portion 402A. A portion of the cavity 408 in the vicinity of the opening has a maximum cavity recess Sc. The process utilized to form the cavity may include a timed processing operation, controlled so as to yield a cavity with a predetermined lateral (X-axis) and vertical dimensions (Y-axis).

In an embodiment, during cavity formation, the Ga atoms that react with the silicon in the substrate also combine with nitrogen, leading to the formation of an alloyed liner 410 that includes at least Ga, Si and N. In an embodiment, the gallium composition in the alloyed liner 410 is between 20 atomic percent and 50 atomic percent. The alloyed liner 410 is formed on the surface of the substrate 104 in the cavity 408 (surface liner portion 410A), on the exposed lower most cantilevered portion of the III-N material 402, on sidewalls of the III- N material 402 (sidewall liner portion 410B) in the opening 406 and on an uppermost surface of the III-N material 402 (uppermost liner portion 410C). In an embodiment, the alloyed liner 410 has a thickness between 50nm-l00nm in the cavity. Silicon is removed from the substrate through the opening 406 during the formation of the alloyed liner 410. The uppermost liner portion 410C may have a greater thickness than the alloyed liner 410 in the cavity 408. Furthermore, the uppermost liner portion 410C may also have a non-uniform thickness with large scale undulations between l00-l50nm. Compositionally, the alloyed liner 410C may have a different Ga content than the surface liner portion 410A or the sidewall liner portion 410B. In one embodiment, when the opening 406 has a width that is approximately two times the width of the alloyed liner 410. The opening 406 may be sealed with the material of the liner during the formation of the cavity 408. Such a self-limiting process may be utilized to control the depth, Sc, and the lateral spatial extent of the cavity In one embodiment, as is depicted in Figure 4D, the cavity is formed laterally apart from the first electrode 110. In other embodiments, the cavity may be directly adjacent to the first electrode 110. In one such embodiment, the alloyed liner 410 will also be formed on a sidewall of the metal electrode 110.

Figure 4E illustrates a cross-sectional view of the structure of Figure 4D following the formation of a dielectric layer 412 on the alloyed liner 410 in the cavity 408, on the uppermost liner portion 410C and filling the opening 406. In an embodiment, the dielectric layer 412 is deposited by a PECVD, PVD or a CVD process. The deposition process may fill the entire cavity 408 with the dielectric layer 412 or may form voids in some portions away from the opening 406. Examples of the dielectric layer 412 may include a material such as, but not to, limited silicon dioxide, silicon nitride, silicon oxynitride, carbon doped nitride and carbon doped oxide.

Figure 4F illustrates a cross-sectional view of the structure of Figure 4E following the planarization of the dielectric layer 412 and the uppermost liner portion 410C. In an embodiment, a polish process is utilized to planarize the oxide and the uppermost liner portion 410C. In an embodiment, the polish process begins by removing the dielectric layer 412 from above the uppermost liner portion 410C and is continued until the uppermost liner portion 410C also completely removed. In one embodiment, a portion of the III-N material 402 is also removed during the polish process. The sidewall alloyed liner portion 410B and a portion of the dielectric 412 remains in the opening 406. In other embodiments, a portion of the liner 410C may remain on the III-N material 402.

Figure 4G illustrates a cross-sectional view of the structure of Figure 4F following the formation of a second electrode on the layer of the PI-N material 402 in the vicinity of the cavity 408. In an embodiment, a layer of metal that is the same or substantially the same as the layer of metal of the first electrode 110 is deposited on the uppermost surface of the III-N material, on the uppermost portion of the sidewall alloyed liner portion 410B, and on the dielectric layer 412 in the opening 406. The layer of metal is then patterned to form the second electrode 112.

Figure 4H illustrates a cross-sectional view of the structure of Figure 4G following the formation of a second dielectric layer 414 on the sidewall alloyed liner portion 410B and on the second electrode 112, in accordance with an embodiment of the present disclosure. In an embodiment, the second dielectric layer 414 includes a material that is the same or substantially the same as the dielectric layer 412. In an embodiment, the second dielectric layer 412 is deposited to a thickness to enable patterning of the III-N to form a resonator. Figure 41 illustrates a plan-view of the structure of Figure 4H following the formation of an opening to form a contact on the first electrode 110, in accordance with an embodiment of the present disclosure. In an embodiment, a resist pattern is formed on the second dielectric layer 414. The resist pattern forms a mask that defines the location for an opening 416 in the second dielectric layer 414 above an extended portion of the first electrode 110 (indicated by the dashed lines 111. In an embodiment, the opening 416 is formed in the second dielectric layer 414 by a plasma etch process. The plasma etch process exposes the underlying III-N material 402. In one embodiment, the resist mask is removed after the second dielectric layer 414 is patterned but prior to etching the III-N material 402 In an embodiment, the resist mask 221 is removed using an ash process. The plasma etch process is then continued to etch the III-N material 402 and expose the underlying first electrode 110 as is depicted in Figure 41. The plan-view of Figure 41 also illustrates the outline 120 of the cavity 408 and an outline of the opening 406.

Figure 4J illustrates a plan-view of the structure of Figure 41 following the formation of a contact 118 to couple with the first electrode 110. In an embodiment, an isolation layer 118 is blanket deposited in the opening 416 and on the uppermost surface of the second dielectric layer 414. The isolation layer 118 is subsequently etched to expose an uppermost surface of the first electrode 110. In a subsequent processing operation, one or more layers of metal are deposited into the opening 416 on the first electrode 110, and on exposed surfaces of the isolation layer 118 and on the surface of the second dielectric layer 414. The layer of metal is then removed from the surface of the second dielectric layer 414 to form a contact 118. In one embodiment, planarization is performed utilizing a polish process to form the contact 118.

Figure 4K illustrates a plan-view of the structure of Figure 4J following the patterning of the layer of the III-N material 402 to form a beam structure, in accordance with an embodiment of the present disclosure. In an embodiment, a third dielectric layer 418 is blanket deposited on the second dielectric layer 414 and over the contact 118. In an embodiment, the third dielectric layer 418 includes a material that is the same or substantially the same as the second dielectric layer 414. The third dielectric layer 418 protects the contact 118 during patterning of the III-N material 402. The patterning process includes patterning the third dielectric layer 418 and then using the patterned third dielectric layer 418 to etch a pattern in the III-N material 402. In the illustrative embodiment, the patterned third dielectric layer 418 includes a single beam structure such as the single beam structure 108B described in association with Figure 1B. The patterning process forms an opening that exposes the underlying dielectric layer 412. In the illustrative embodiment, the location of the opening coincides with the location of opening 406. In one such embodiment, the sidewall liner portion 410B is also removed during etching of the III-N material 402.

Figure 4L illustrates a cross-sectional view of the structure of Figure 4K, along a line B-B’, following the removal of the dielectric layers 418, 414 and 412. In an embodiment, the dielectric layers 418, 414 and 412 include a silicon oxide. The removal of the silicon oxide may be facilitated by a wet chemical etch process that removes the silicon dioxide selectively with respect to the III-N material 402, the isolation 118, the contact 116, and the liner 410. The removal of the dielectric layer 402 from under the III-N material 402 leads to the formation of the cantilevered beam structure 108B above the cavity 402.

Figure 5 illustrates a cross-sectional view of a device system 500 including the resonator 100 adjacent to a III-N transistor 501 above the substrate 104. transistor 501 includes a channel layer 502 having a IP-N material, and a polarization charge inducing layer 504 including a III-N material above the channel layer 502. The channel layer is adjacent to the material of the cantilevered structure 108. The polarization charge inducing layer 504 induces a 2-dimensional electron gas (2DEG is indicated by the dashed lines 513) within channel layer 502 near an interface between the polarization charge inducing layer 504 and the channel layer 502. The 2DEG enables a portion of the channel layer 502 to become electrically active. The transistor 501 further includes a gate 506 above the polarization charge inducing layer 504, a source structure 508 on one side of the gate 506 and a drain structure 510 on another side of gate 506 opposite the source structure 508. The gate 506, further includes a gate dielectric layer 506A on the polarization charge inducing layer 504 and a gate electrode 506B on the gate dielectric layer 506A as illustrated in Figure 5B. The transistor further includes a source contact 518 on and coupled to the source structure 508, a drain contact 520 on and coupled to the drain structure 510. An isolation 516A is between the channel layer 502 of the transistor 501 and the material of the cantilevered structure 108. In an embodiment, isolation has a width, Wi. In an embodiment, Wj, is between lpm-lOpm and provides adequate electrical isolation between the transistor 501 and the resonator 100. An isolation 516B is distal from isolation 516A and adj acent to the drain structure 510 and the channel layer 502.

In the illustrative embodiment, the channel layer 502 has a thickness T _T in the transistor 501 that is approximately equal to a thickness Ts of the structural member 108. A thickness T, equal to thickness Tp may be indicative of selective formation of the channel layer 502. In an embodiment, the channel layer 502 includes a gallium nitride (GaN) alloy. In one such embodiment, the channel layer 502 has a relatively high carrier mobility, (greater than 500 cm ² V ¹ ). The channel layer 502 may be a substantially un-doped III-N material (i.e., 0 ₂ impurity concentration minimized) for minimal impurity scattering. In other embodiments, the channel layer 502 includes one or more ternary alloys of GaN, such as AlGaN, AlInN, or a quaternary alloy of GaN including at least one group III element and nitrogen, such as In _x Al _y Gai- _x-y N, where x ranges from 0.01-0.1 and y ranges from 0.01-0.1. Depending on applications, the channel layer 502 has a material thickness approximately in the range of 500nm-5um.

In an embodiment, the polarization charge inducing layer 504 includes a suitable III-N material. In an embodiment, the polarization charge inducing layer 504 includes a material such as but not limited to Al _z Gai_ _z N, Al _w Ini_ _w N, or AIN, where Z ranges from 0.2-0.3 and W ranges from 0.7-0.85. One combination includes a polarization charge inducing layer 504 that is AlGaN and a channel layer 502 that is GaN. In one such combination, the AlGaN polarization charge inducing layer 504 has a bandgap (3.7 eV) that is wider than the bandgap of the GaN III-N material 502 (3.4 eV), facilitating a band offset at the interface between the AlGaN polarization charge inducing layer 504 and the GaN III-N material 502. The presence of the 2DEG enables current conduction between the source structure 508 and the drain structure 510 in the device 500. In the illustrated embodiment, by negatively biasing the gate electrode 506 relative to the drain contact 510, the 2DEG is turned off.

The gate dielectric layer 506A may have a high relative permittivity (i.e., dielectric constant, K). In some high-K gate dielectric embodiments, the gate dielectric layer 506A is a metal oxide (e.g., including oxygen and one or more metals, such as, but not limited to, aluminum, hafnium, zirconium, tantalum or titanium). In another embodiment, the gate dielectric layer 506A includes a silicon dioxide or a silicon nitride. In some examples, the gate dielectric layer 506A has a thickness between 2nm and 50 nm.

In an embodiment, the gate electrode 506B includes a metal such as but not limited to Pt, Ni and an alloy such as TiN or TaN. In one such embodiment, the gate electrode 506B has a length, LQ, approximately in the range of 50-30nm. In some embodiments, the gate electrode 506B further includes a work function metal and a gate cap. The work function metal may include a metal such as Pt, Ni, and an alloy such as TiN or TaN and the gate cap may include a metal such as W.

In an embodiment, the source structure 508 and drain structure 510, have uppermost surfaces that are above the level of the polarization charge inducing layer 504 and the isolation layer 518. In an embodiment, the source structure 508, drain structure 510 include a third III-N material that is lattice matched to the channel layer 502 of the channel layer 502.

In one exemplary embodiment, where the channel layer 502 is GaN the source structure 508, drain structure 510 includes a single crystal of InGaN. In the illustrative embodiment, the source structure 508 and the drain structure 510 include faceted crystals having sidewalls that are approximately 60 degrees with respect to a plane of the layer of the substrate 104.

In an exemplary embodiment, the third III-N material includes an impurity dopant such as an n-type dopant. Examples of an n-type dopant includes a material such as Si or Ge. In one embodiment, the n-type dopant material is silicon As a further example, the silicon n- type dopant may have a n-dopant density of at least lel9/cm ³ . Doping of the source structure 508 can reduce the bandgap between the source contact 508 and the source structure 508. Likewise, doping of the drain structure 510 can reduce the bandgap between drain contact 520 and the drain structure 510. A reduced bandgap may lead to a reduced contact resistance of the device 500.

In an embodiment, the source contact 518, and the drain contact 520 each include a multi-layer stack. In an embodiment, the multi-layer stack includes two or more distinct layers of metal such as a layer of Ti, Ru or A1 and a conductive cap on the layer of metal.

The conductive cap may include a material such as W or Cu.

Examples of the isolation 516A and 516B may include any material that has sufficient dielectric strength to provide electrical isolation such as, but not to, limited silicon dioxide, silicon nitride, silicon oxynitride, carbon doped nitride and carbon doped oxide.

In an embodiment, the channel layer 502 is on a buffer layer (not shown). In an embodiment, the buffer layer includes a III-N material such as but not limited to Al _z Gai_ _z N, Al _w Ini_ _w N, or AIN. In an embodiment, the buffer layer minimizes crystal defects in the channel layer 502 that would ordinarily arise from lattice mismatch between the channel layer 502 and the underlying substrate 104. In an embodiment, the buffer layer 132 has a thickness that is at least 500nm.

In an exemplary embodiment, the substrate 104 is a silicon substrate having a (100) top surface. A silicon substrate with a (100) top surface enables co-integration of an additional silicon CMOS transistor technology with a III-N material. In a second

embodiment, a silicon substrate, has a (111) top surface. In some embodiments, the buffer layer and the substrate 104 have mismatched lattice structures. The lattice mismatch between the buffer layer and the substrate 104 may be between 15% - 50%.

Figure 6 illustrates a system 600 in which a mobile computing platform 605 and/or a data server machine 606 employs an integrated circuit (IC) 650 including a device system 500 having a transistor 501 and a resonator 100. The server machine 606 may be any commercial server, for example including any number of high-performance computing platforms disposed within a rack and networked together for electronic data processing, which in the exemplary embodiment includes a packaged monolithic IC 650. The mobile computing platform 605 may be any portable device configured for each of electronic data display, electronic data processing, wireless electronic data transmission, or the like. For example, the mobile computing platform 605 may be any of a tablet, a smart phone, laptop computer, etc., and may include a display screen (e.g., a capacitive, inductive, resistive, or optical touchscreen), a chip-level or package-level integrated system 610, and a battery 615.

Whether disposed within the integrated system 610 illustrated in the expanded view 620, or as a stand-alone packaged chip within the server machine 606, packaged monolithic IC 650 includes a memory chip (e.g., RAM), or a processor chip (e.g., a microprocessor, a multi-core microprocessor, graphics processor, or the like) including at least one device system, such as device system 500 having a transistor 501 and a resonator 100 for example, as describe in Figure 5. The monolithic IC 650 may be further coupled to a board, a substrate, or an interposer 660 along with, one or more of a power management integrated circuit (PMIC) 630, RF (wireless) integrated circuit (RFIC) 625 including a wideband RF (wireless) transmitter and/or receiver (TX/RX) (e.g., including a digital baseband and an analog front end module further comprises a power amplifier on a transmit path and a low noise amplifier on a receive path), and a controller thereof 635.

Functionally, PMIC 630 may perform battery power regulation, DC-to-DC conversion, etc., and so has an input coupled to battery 615 and with an output providing a current supply to other functional modules. As further illustrated, in the exemplary embodiment, RFIC 625 has an output coupled to an antenna (not shown) to implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. In alternative implementations, each of these board-level modules may be integrated onto separate ICs coupled to the package substrate of the monolithic IC 650 or within a single IC coupled to the package substrate of the monolithic IC 650. Figure 7 illustrates a computing device 700 in accordance with embodiments of the present disclosure. As shown, computing device 700 houses a motherboard 702.

Motherboard 702 may include a number of components, including but not limited to a processor 701 and at least one communication chip 705. Processor 701 is physically and electrically coupled to the motherboard 702. In some implementations, communication chip 705 is also physically and electrically coupled to motherboard 702. In further

implementations, communication chip 705 is part of processor 701.

Depending on its applications, computing device 700 may include other components that may or may not be physically and electrically coupled to motherboard 702. These other components include, but are not limited to, volatile memory (e g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset 706, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).

Communication chip 705 enables wireless communications for the transfer of data to and from computing device 700. The term“wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. Communication chip 705 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.11 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. Computing device 700 may include a plurality of communication chips 704 and 705. For instance, a first communication chip 705 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 704 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

Processor 701 of the computing device 700 includes an integrated circuit die packaged within processor 701. In some embodiments, the integrated circuit die of processor 701 includes a device system 500 having a transistor 501 and a resonator 100. The term “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

Communication chip 705 also includes an integrated circuit die packaged within communication chip 706. In another embodiment, the integrated circuit die of

communication chip 705 includes a memory array with memory cells including a transistor such as transistor 501 and a non-volatile memory device coupled to transistor 501. The non volatile memory device may include a magnetic tunnel junction (MTJ) device, a resistive random access memory (RRAM) device or a conductive bridge random access memory (CBRAM) device.

In various examples, one or more communication chips 704, 705 may also be physically and/or electrically coupled to the motherboard 702 In further implementations, communication chips 704 may be part of processor 701. Depending on its applications, computing device 700 may include other components that may or may not be physically and electrically coupled to motherboard 702. These other components may include, but are not limited to, volatile memory (e.g., DRAM) 707, 708, non-volatile memory (e.g., ROM) 710, a graphics CPU 712, flash memory, global positioning system (GPS) device 713, compass 714, a chipset 706, an antenna 716, a power amplifier 709, a touchscreen controller 711, a touchscreen display 717, a speaker 715, a camera 703, and a battery 718, as illustrated, and other components such as a digital signal processor, a crypto processor, an audio codec, a video codec, an accelerometer, a gyroscope, and a mass storage device (such as hard disk drive, solid state drive (SSD), compact disk (CD), digital versatile disk (DVD), and so forth), or the like. In further embodiments, any component housed within computing device 700 and discussed above may contain a stand-alone integrated circuit memory die that includes one or more arrays of memory cells 300 and/or transistor 100, built in accordance with embodiments of the present disclosure.

In various implementations, the computing device 700 may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra- mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top b04, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device 700 may be any other electronic device that processes data.

Figure 8 illustrates an integrated circuit structure 800 that includes one or more embodiments of the disclosure. The integrated circuit (IC) structure 800 is an intervening structure used to bridge a first substrate 802 to a second substrate 804. The first substrate 802 may be, for instance, an integrated circuit die. The second substrate 804 may be, for instance, a memory module, a computer mother, or another integrated circuit die. The integrated circuit die may include one or more device systems such as a device system 500 having a transistor 501 and a resonator 100, for example. Generally, the purpose of an integrated circuit (IC) structure 800 is to spread a connection to a wider pitch or to reroute a connection to a different connection. For example, an integrated circuit (IC) structure 800 may couple an integrated circuit die to a ball grid array (BGA) 806 that can subsequently be coupled to the second substrate 804. In some embodiments, the first and second substrates 802/804 are attached to opposing sides of the integrated circuit (IC) structure 800. In other embodiments, the first and second substrates 802/804 are attached to the same side of the integrated circuit (IC) structure 800. And in further embodiments, three or more substrates are interconnected by way of the integrated circuit (IC) structure 800.

The integrated circuit (IC) structure 800 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In further implementations, the integrated circuit (IC) structure 800 may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III- N, group III-V and group IV materials

The integrated circuit (IC) structure 800 may include metal interconnects 808 and via 810, including but not limited to through-silicon vias (TSVs) 810. The integrated circuit (IC) structure 800 may further include embedded devices 814, including both passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, III-N transistors such as the transistor 501 adjacent to resonator 100, one or more magnetic tunnel junction or resistive random-access devices, sensors, and electrostatic discharge (ESD) devices. More complex devices such as radio-frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the integrated circuit (IC) structure 800. In accordance with embodiments of the present disclosure, apparatuses or processes disclosed herein may be used in the fabrication of integrated circuit (IC) structure 800.

As used in any implementation described herein, the term“module” refers to any combination of software, firmware and/or hardware configured to provide the functionality described herein. The software may be embodied as a software package, code and/or instruction set or instructions, and“hardware”, as used in any implementation described herein, may include, for example, singly or in any combination, hardwired circuitry, programmable circuitry, state machine circuitry, and/or firmware that stores instructions executed by programmable circuitry. The modules may, collectively or individually, be embodied as circuitry that forms part of a larger system, for example, an integrated circuit (IC), system on-chip (SoC), and so forth.

While certain features set forth herein have been described with reference to various implementations, this description is not intended to be construed in a limiting sense. Hence, various modifications of the implementations described herein, as well as other

implementations, which are apparent to persons skilled in the art to which the present disclosure pertains are deemed to lie within the spirit and scope of the present disclosure.

Thus, embodiments of the present disclosure include group Ill-Nitride (III-N) resonators and methods of fabrication.

In a first example, device includes a cavity in a substrate where the substrate includes a group IV material. The device further includes a liner on a surface of the substrate within the cavity where the liner includes a group III material, the group IV material and nitrogen. A structural member, including a III-N material, is cantilevered over the cavity. An electrode structure is coupled to the structural member.

In second examples, for any of first examples, the group IV includes silicon.

In third examples, for any of the first through second examples, the group III material is crystalline and includes Gallium.

In fourth examples, for any of the first through third examples, the III-N material is crystalline and includes Al.

In fifth examples, for any of the first through fourth examples, the structural member includes one or more beams.

In sixth examples, for any of the first through fifth examples, a separation between a surface of the structural member and the surface of the substrate within the cavity varies along a length of the structural member.

In seventh examples, for any of the first through sixth examples, the separation has a maximum value at a center of the cavity and a minimum value near a perimeter edge of the cavity.

In eighth examples, for any of the first through seventh examples, the separation at the center is at least 1 mi cron.

In ninth examples, for any of the first through eighth examples, the cavity has a lateral dimension between IOmhi and IOOmhi.

In tenth examples, for any of the first through ninth examples, the structural member is a trilayer stack including the liner, the III-N material and a layer including the liner on the III-N material.

In eleventh examples, for any of the first through tenth examples, the liner includes an alloy including gallium, silicon and nitrogen and having a gallium composition between 20 atomic percent and 50 atomic percent.

In twelfth examples, for any of the first through eleventh examples, the liner has a thickness between lOnm-lOOnm.

In thirteenth examples, for any of the first through twelfth examples, the liner is adjacent to a lowermost surface of the structural member.

In a fourteenth example, for any of the first through thirteenth examples, the liner includes a non-uniform thickness along the surface of the cavity and along a lowermost surface of the structural member, wherein the thickness varies by up to 50% along the surface of the cavity and along the lowermost surface of the structural member

In a fifteenth example, a method of fabricating a device includes forming a first layer including a first Ill-nitride (III-N) material above a substrate. The method further includes patterning the first layer to form an opening. The method further includes depositing a second layer including a second III-N material over the first layer. The method of depositing forms an alloy of a material of the substrate and the material of the second layer, forms a cavity in the substrate under the first layer, forms a liner on a surface of the substrate within the cavity, and forms a cantilevered structural member including the first layer and exposes the cavity. The method further includes forming an electrode above the cavity and coupling the electrode to the cantilevered structural member.

In sixteenth examples, for any of the fifteenth examples, forming the alloy includes depositing the alloy over the first layer.

In seventeenth examples, for any of the fifteenth through sixteenth examples, forming the liner includes reacting a group III material with a material of the substrate and forming a layer having a non-uniform thickness.

In eighteenth examples, for any of the fifteenth through seventeenth examples, forming the electrode includes depositing a dielectric layer on the second layer and in the cavity through the opening in the first layer, planarizing the dielectric layer and the alloy, depositing a layer of conductive material over the first layer, patterning an electrode over the first layer and removing the dielectric layer. In nineteenth examples, for any of the fifteenth through eighteenth examples, forming the electrode includes planarizing and removing the alloy and forming the electrode on the first layer

In a twentieth example, for any of the fifteenth through nineteenth examples, forming the cantilevered structural member includes forming a hardmask layer on the first layer, patterning the hardmask layer, patterning the first layer to expose portions of the substrate and removing the hardmask layer after pattering the first layer.

In a twenty first example, device includes a resonator in a portion of a substrate and a transistor over the substrate. The resonator includes a cavity in a substrate where the substrate includes a group IY material. The device further includes a liner on a surface of the substrate within the cavity where the liner includes a group III material, the group IV material and nitrogen. A structural member, including a III-N material, is cantilevered over the cavity. An electrode structure is coupled to the structural member. The transistor includes a first layer having a second III-N material, and further includes a polarization charge inducing layer above the first layer. The polarization charge inducing layer includes a second III-N material. The transistor further includes a gate electrode above the polarization charge inducing layer and a source structure and a drain structure on the first layer on opposite sides of the gate electrode.

In twenty second examples, for any of the twenty first examples, the group IV material includes silicon, wherein the group III material is crystalline and includes Gallium, and wherein the III-N material is crystalline and includes Al.

In twenty third examples, for any of the twenty first through twenty second examples, the structural member includes one or more beams.

In twenty fourth examples, for any of the twenty first through twenty third examples, the second IP-N material includes Ga.

In twenty fifth examples, for any of the twenty first through twenty fourth examples, the source structure and a drain structure include a third doped III-N material.