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Title:
GROUP III-NITRIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
Document Type and Number:
WIPO Patent Application WO/2011/016940
Kind Code:
A3
Abstract:
Methods of forming Group III-nitride transistor device include forming a protective layer on a Group III-nitride semiconductor layer, forming a via hole through the protective layer to expose a portion of the Group III-nitride semiconductor layer, and forming a masking gate on the protective layer. The masking gate includes an upper portion having a width that is larger than a width of the via hole and having a lower portion extending into the via hole. The methods further include implanting source/drain regions in the Group III-nitride semiconductor layer using the masking gate as an implant mask.

Inventors:
SMITH R PETER (US)
SHEPPARD SCOTT T (US)
Application Number:
PCT/US2010/041202
Publication Date:
May 19, 2011
Filing Date:
July 07, 2010
Export Citation:
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Assignee:
CREE INC (US)
SMITH R PETER (US)
SHEPPARD SCOTT T (US)
International Classes:
H01L21/266; H01L21/335; H01L21/285; H01L21/338; H01L29/20; H01L29/423; H01L29/778; H01L29/812; H01L29/15
Foreign References:
US4929567A1990-05-29
US20070164321A12007-07-19
Other References:
KAMECHE M ET AL: "High-Temperature Distortion and Power-Handling Properties of GaAs-, 4H-SiC-, GaN- MESFET's Switches", ELECTROTECHNICAL CONFERENCE, 2006. MELECON 2006. IEEE MEDITERRANEAN BENALMADENA, SPAIN 16-19 MAY 2006, PISCATAWAY, NJ, USA,IEEE LNKD- DOI:10.1109/MELCON.2006.1653063, 16 May 2006 (2006-05-16), pages 169 - 172, XP010927716, ISBN: 978-1-4244-0087-4
K. YAMASAKI, K. ASAI, K. KURUMADA: "N+ Self-aligned MESFET for GaAs LSIs", JAPANESE JOURNAL OF APPLIED PHYSICS, vol. 22, 1 January 1983 (1983-01-01) - 31 December 1983 (1983-12-31), Tokyo, JP, pages 381 - 384, XP001491212
Attorney, Agent or Firm:
MYERS BIGEL SIBLEY & SAJOVEC, P.A. (Raleigh, North Carolina, US)
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