Title:
HARDWARE ARCHITECTURE FOR ACCELERATION OF COMPUTER VISION AND IMAGING PROCESSING
Document Type and Number:
WIPO Patent Application WO/2017/150811
Kind Code:
A1
Abstract:
An image and vision processing architecture included a plurality of image processing hardware accelerators each configured to perform a different one of a plurality of image processing operations on image data. A multi-port memory shared by the hardware accelerators stores the image data and is configurably coupled by a sparse crossbar interconnect to one or more of the hardware accelerators depending on a use case employed. The interconnect processes accesses of the image data by the hardware accelerators. Two or more of the hardware accelerators are chained to operate in sequence in a first order for a first use case, and at least one of the hardware accelerators is set to operate for a second use case. Portions of the memory are allocated to the hardware accelerators based on the use case employed, with an allocated portion of the memory configured as a circular buffer.
Inventors:
LEE SEOK-JUN (US)
LEE SEUNGJIN (US)
LEE SEUNGJIN (US)
Application Number:
PCT/KR2017/001028
Publication Date:
September 08, 2017
Filing Date:
January 31, 2017
Export Citation:
Assignee:
SAMSUNG ELECTRONICS CO LTD (KR)
International Classes:
G06T1/20; G06T1/60
Foreign References:
| US20150046677A1 | 2015-02-12 | |||
| US20150317190A1 | 2015-11-05 | |||
| US7636817B1 | 2009-12-22 | |||
| KR20070119692A | 2007-12-20 | |||
| JP2011520166A | 2011-07-14 | |||
| US20140240327A1 | 2014-08-28 | |||
| US20150235341A1 | 2015-08-20 | |||
| US20110080404A1 | 2011-04-07 |
Other References:
See also references of EP 3414733A4
Attorney, Agent or Firm:
KWON, Hyuk-Rok et al. (KR)
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