Title:
HARDWARE QUADRATIC PROGRAMMING SOLVER AND METHOD OF USE
Document Type and Number:
WIPO Patent Application WO/2012/076838
Kind Code:
A3
Abstract:
A quadratic programming solver architecture comprising: a first hardware block arranged to perform parallel dot-product operations and thereby carry out matrix-vector multiplication, the first hardware block comprising a plurality of parallel multipliers and an adder tree arranged to combine the outputs from the parallel multipliers; a second hardware block comprising arithmetic processing means arranged to receive input data comprising constants and variables and to perform scalar operations thereon, the output from the arithmetic processing means being arranged to supply the parallel multipliers of the first hardware block, the variables being output from the first hardware block and fed back to the second hardware block; and control means configured to selectively schedule the sequence of scalar operations performed by the arithmetic processing means.
Inventors:
CONSTANTINIDES GEORGE ANTHONY (GB)
KERRIGAN ERIC COLIN (GB)
JEREZ FULLANA JUAN LUIS (GB)
KERRIGAN ERIC COLIN (GB)
JEREZ FULLANA JUAN LUIS (GB)
Application Number:
PCT/GB2011/001679
Publication Date:
September 27, 2012
Filing Date:
December 02, 2011
Export Citation:
Assignee:
IMP INNOVATIONS LTD (GB)
CONSTANTINIDES GEORGE ANTHONY (GB)
KERRIGAN ERIC COLIN (GB)
JEREZ FULLANA JUAN LUIS (GB)
CONSTANTINIDES GEORGE ANTHONY (GB)
KERRIGAN ERIC COLIN (GB)
JEREZ FULLANA JUAN LUIS (GB)
International Classes:
G06F7/544
Other References:
S. J. WRIGHT: "Applying new optimization algorithms to model predictive control", PROC. INT. CONF. CHEMICAL PROCESS CONTROL, 1 January 1997 (1997-01-01), pages 147 - 155, XP055030444, Retrieved from the Internet [retrieved on 20120620]
DAVID BOLAND ET AL: "An FPGA-based implementation of the MINRES algorithm", FIELD PROGRAMMABLE LOGIC AND APPLICATIONS, 2008. FPL 2008. INTERNATIONAL CONFERENCE ON, IEEE, PISCATAWAY, NJ, USA, 8 September 2008 (2008-09-08), pages 379 - 384, XP031324382, ISBN: 978-1-4244-1960-9
DAVID BOLAND ET AL: "Optimising Memory Bandwidth Use for Matrix-Vector Multiplication in Iterative Methods", 17 March 2010, RECONFIGURABLE COMPUTING: ARCHITECTURES, TOOLS AND APPLICATIONS, SPRINGER BERLIN HEIDELBERG, BERLIN, HEIDELBERG, PAGE(S) 169 - 181, ISBN: 978-3-642-12132-6, XP019139327
MINGHUA HE ET AL: "Model Predictive Control On A Chip", CONTROL AND AUTOMATION, 2005. ICCA '05. INTERNATIONAL CONFERENCE ON BUDAPEST, HUNGARY 26-29 JUNE 2005, PISCATAWAY, NJ, USA,IEEE, vol. 1, 26 June 2005 (2005-06-26), pages 528 - 532, XP010849799, ISBN: 978-0-7803-9137-6, DOI: 10.1109/ICCA.2005.1528175
FLORIAN A. POTRA ET AL: "Interior-Point Methods", 10 February 2000 (2000-02-10), XP055030453, Retrieved from the Internet [retrieved on 20120620]
DAVID BOLAND ET AL: "An FPGA-based implementation of the MINRES algorithm", FIELD PROGRAMMABLE LOGIC AND APPLICATIONS, 2008. FPL 2008. INTERNATIONAL CONFERENCE ON, IEEE, PISCATAWAY, NJ, USA, 8 September 2008 (2008-09-08), pages 379 - 384, XP031324382, ISBN: 978-1-4244-1960-9
DAVID BOLAND ET AL: "Optimising Memory Bandwidth Use for Matrix-Vector Multiplication in Iterative Methods", 17 March 2010, RECONFIGURABLE COMPUTING: ARCHITECTURES, TOOLS AND APPLICATIONS, SPRINGER BERLIN HEIDELBERG, BERLIN, HEIDELBERG, PAGE(S) 169 - 181, ISBN: 978-3-642-12132-6, XP019139327
MINGHUA HE ET AL: "Model Predictive Control On A Chip", CONTROL AND AUTOMATION, 2005. ICCA '05. INTERNATIONAL CONFERENCE ON BUDAPEST, HUNGARY 26-29 JUNE 2005, PISCATAWAY, NJ, USA,IEEE, vol. 1, 26 June 2005 (2005-06-26), pages 528 - 532, XP010849799, ISBN: 978-0-7803-9137-6, DOI: 10.1109/ICCA.2005.1528175
FLORIAN A. POTRA ET AL: "Interior-Point Methods", 10 February 2000 (2000-02-10), XP055030453, Retrieved from the Internet
Attorney, Agent or Firm:
PITCHFORD, James Edward et al. (20 Red Lion Street, London WC1R 4PJ, GB)
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