FIELD OF THE INVENTION

The present invention relates to a direct conversion receiver that receives a load modulated analog input signal in the HF frequency area and outputs digital data detected in the input signal, which receiver comprises: a transmitter to emit a magnetic field with a carrier frequency signal; a carrier signal stage to provide the carrier frequency signal which is in frequency and phase synchronized to the carrier frequency signal received in the input signal; an in-phase mixer that mixes the input signal with an in-phase carrier frequency signal and provides an in-phase component of a down-converted input signal in the baseband frequency area with unwanted harmonic multiples; and a quadrature-phase mixer that mixes the input signal with a quadrature-phase carrier frequency signal and provides a quadrature-phase component of a down-converted input signal in the baseband frequency area with unwanted harmonic multiples; an in-phase amplifier to amplify the in-phase component of the down-converted input signal and a quadrature-phase amplifier to amplify the quadrature-phase component of the down- converted input signal; two parallel units connected parallel to each of the amplifiers, which parallel units comprise a capacity and a ohmic resistance connected parallel to each other to filter and to transform the in-phase component and the quadrature-phase component from the current domain into the voltage domain.

BACKGROUND OF THE INVENTION

Document EP 3 168 772 Bl discloses such a receiver that is used for radio frequency identification (RFID) devices like RFID readers to communicate with active or passive transponders. In a typical application a passive transponder or tag stores product identification of a product to which it is attached and the reader is used to obtain this product information. The reader is powered and generates a magnetic field from its antenna. When the reader and the tag are within close proximity of each other, the reader generated magnetic field is induced into the antenna of the tag and used to power the tag. The tag also has a transceiver to receive the signal from the reader and to transmit a response back to the reader. There are standards like ISO/IEC 18000-3 or ISO/IEC 14.443 Type A and B or ISO15.693 or ECMA-340 13,56 MHz Near Field Communication (NFC) or company standards like Felica from company Sony that define protocols and types of modulation used to transmit information between the tag and the reader. Some or all of these standards define that the reader transmits data to the tags by changing the magnitude of its transmitted power. Tags receive the transmitted signal and process the received data. The activated tag then replies by transmitting data to the reader. A typical technique is to use load modulation, in which the tag varies the load impedance of its coil by changing its resonance frequency and its quality factor. This action causes a voltage variation at the reader antenna. The receiver of the reader disclosed in figure 2 of document EP 3 168 772 Bl processes such load modulated analog input signals in the HF frequency area to output digital data detected in the input signal. A matching circuit is connected between the HF antenna and the input of a mixer stage to provide a load modulated analog input signal and an impedance between the matching circuit and the mixer stage is used to convert the load modulated analog input signal into the current domain. “Current domain” in this application is understood in that sense that the information of the input signal is provided as input current while “voltage domain” is understood in that sense that the information of the input signal is provided as input voltage.

Prior art reader known to a person skilled in the art use a mixer stage 1 like the one disclosed in figure 1 of the pending application that receives the load modulated analog input signal 2 in the current domain. Mixer stage 1 of such known receiver comprises an in-phase mixer 3 that mixes the input signal 2 with an in-phase carrier frequency signal 4 provided by a carrier signal stage not shown in figure 1. The carrier signal stage provides the carrier signal which is in frequency and phase synchronized to the carrier signal received in the input signal of the receiver. Only this synchronized carrier signal enables a direct conversion receiver that uses its mixer stage to convert the received load modulated analogue input signal from the HF frequency area of e.g. 13,56MHz into the base band frequency area. After this conversion the load modulated input signal may be further processed in the base band frequency area by the receiver to output digital data detected in the input signal.

In-phase mixer 3 provides an in-phase component of a down-converted input signal 5 mixed with the carrier signal 4 with a phase shift of 0° at output connection 6 of the in-phase mixer 3. In-phase mixer 3 furthermore provides an in-phase component of a down-converted input signal 8 mixed with the carrier signal 4 with a phase shift of 180° at output connection 7 of the in-phase mixer 3. These in-phase down-converted input signals 5 and 8 comprise the received wanted information 27 of the load modulated input signal in the baseband frequency area and furthermore comprise unwanted harmonic multiples of the carrier signal as a result of the mixing. The received wanted information 27 is for instance within a bandwidth of about 2 MHz while the unwanted harmonic multiples are at multiples of the carrier signal so for instance at 27,12 MHz, 54,24 MHz and so on as can be seen in figure 3.

Mixer stage 1 furthermore comprises an in-phase amplifier 9 which is built as a differential amplifier to amplify the difference signal between the in-phase down-converted input signals 5 and 8. Amplified in-phase output signals of the in-phase amplifier 9 are provided on a negative and a positive output connection of in-phase amplifier 9 and form an in-phase output signal BBI of the mixer stage 1.

Mixer stage 1 furthermore comprises two parallel units 10 connected parallel to the in-phase amplifier 9. One of the parallel units 10 is connected to a positive input and a negative output of the in-phase amplifier 9 and another one of the parallel units 10 is connected to a negative input and a positive output of the in-phase amplifier 9. The parallel unit 10 comprises a capacity 11 and an ohmic resistance 12 connected parallel to each other. The capacity 11 is realized in the Pico Farad range to realize a low pass filter, which attenuates mixing harmonics as well as limiting the signal bandwidth to suppress noise and close by interferers. The impedance of unit 10 transforms the in-phase component from the current domain back into the voltage domain.

The in-phase mixer 3 and the in-phase amplifier 9 and the two parallel units 10 form an in-phase processing stage for down-converting the in-phase component of the input signal 2. Mixer stage 1 furthermore comprises a quadrature-phase processing stage built identical like the in-phase processing stage to down-convert the quadrature-phase component of the input signal 2. A quadrature-phase mixer 13 mixes the input signal 2 with a quadrature-phase carrier frequency signal 14 with a phase shift of 90° and 270° and provides quadrature-phase components 15 and 16 of a down-converted input signal in the baseband frequency area with unwanted harmonic multiples. A quadrature-phase amplifier 17 amplifies the quadraturephase component 15 and 16 of the down-converted input signal. Amplified quadrature-phase output signals are provided on a negative and a positive output connection of quadraturephase amplifier 17 and form a quadrature-phase output signal BBQ of the mixer stage 1.

State of the art mixer stage 1 furthermore comprises four large shunt capacitors 18 connected to the output connections 6 and 7 of the in-phase mixer 3 and the output connections of the quadrature-phase mixer 13. These shunt capacitors 18 are used to filter the unwanted harmonic multiples of the carrier signal in the down-converted in-phase and quadrature-phase components of the input signal 2, when the loop gain of the amplifiers 9 and 17 decreases or, when the amplifiers 9 and 17 run out of bandwidth. This is effective for components of the down-converted signal far away of the baseband, but not for unwanted harmonic multiples that are relatively close to the wanted signal in the baseband like defined in the NFC Standard. It is therefore a disadvantage of the mixer stage 1 according to the state of the art that the unwanted first harmonic at 27,12 MHz is not filtered good enough. This is particular the case as the input connections of the amplifiers 9 and 17 comprise a relative low impedance of only 20 to 30 Ohm. Therefore the unwanted harmonics, especially the first harmonic, are passed to the outputs BBI and BBQ with low attenuation. In presence of this large harmonics, the post-processing of the wanted information 27 to provide correct digital data detected in the input signal is difficult.

Figure 3 shows the problem of the state of the art direct conversion receiver with mixer stage 1 in three frequency diagrams. The upper diagram 25 in figure 3 shows a frequency diagram of e.g. the in-phase carrier signal 4 with the frequency I'LO of the clock signal LO of 13,56 MHz and sidebands with odd multiples of the clock signal LO. As the clock signal LO is generated from a square wave signal and a differential signal processing is used this clock signal LO only comprises odd multiples of the clock signal LO. As stated above, in the direct conversion receiver the frequency I'LO of the clock signal LO is equal to the frequency fRF of carrier signal received in the load modulated analogue input signal. The middle diagram 26 in figure 3 shows a frequency diagram of the load modulated analog input signal 2 with the received wanted information 27 around the carrier signal RF within a bandwidth of about 2 MHz. The lower diagram 28 in figure 3 shows a frequency diagram of the mixer output signal with the wanted information 27 in the baseband with a relative low amplitude compared to the high amplitudes of the even multiples H2, BB and H4, BB. As stated above this happens as the first odd multiple Hl, LO of the clock signal LO and the first odd multiple of the carrier signal Hl, RF with the wanted information 27 are in the same frequency area. As the amplitude of the first even multiple H2,BB is high compared to the amplitude of the wanted signal 27, amplifiers 9 and 17 are either in saturation with the first even multiple H2,BB or amplify the wanted information 27 not good enough to provide useful output signals BBI and BBQ.

SUMMARY OF THE INVENTION It is an object of the invention to provide a receiver with a mixing stage that provides a better filtering of the unwanted harmonics of the carrier signal and in particular a better filtering of the first harmonic of the carrier signal.

This object is achieved with a receiver that furthermore comprises: a parallel in-phase mixer unit connected parallel, but inverted to the output connections of the in-phase mixer to subtract the unwanted harmonic multiples, which parallel in-phase mixer unit comprises a second in-phase mixer with a serial filter capacity connected at each of its output connections to block the baseband frequency area of the in-phase component of the down-converted input signal; a parallel quadrature-phase mixer unit connected parallel, but inverted to the output connections of the quadrature-phase mixer to subtract the unwanted harmonic multiples, which parallel quadrature-phase mixer unit comprises a second quadrature-phase mixer with a serial filter capacity connected at each of its output connections to block the baseband frequency area of the quadrature-phase component of the down-converted input signal.

The invention is based on the concept to use two parallel identical in-phase mixer, but one with serial filter capacities to only let pass the unwanted harmonics that result from the mixing. These unwanted harmonics are then subtracted from the in-phase down-converted input signals. As a result the in-phase output signal BBI of the mixer stage comprises the wanted load modulated input signal in the baseband frequency area with much lower harmonic content. The same is done in the quadrature-phase path to achieve that the quadrature-phase output signal BBQ of the mixer stage comprises the wanted load modulated input signal in the baseband frequency area with much lower harmonic content.

These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter. The person skilled in the art will understand that various embodiments may be combined.

BRIEF DESCRIPTION OF THE DRAWINGS

Figures 1 shows a mixer stage of a receiver to process a load modulated analog input signal according to the state of the art.

Figure 2 shows a mixer stage of a receiver to process a load modulated analog input signal according to one embodiment of the invention.

Figure 3 shows three frequency diagrams of the state of the art mixer of figure 1. Figure 4 shows the three frequency diagrams of figure 3, but with the subtraction of the output signals of both in-phase mixers and both quadrature-phase mixers.

DETAILED DESCRIPTION OF EMBODIMENTS

Figure 2 shows a mixer stage 19 with a receiver that is part of an RFID reader that is built to receive a load modulated analog input signal 2 and outputs digital data sent from a transponder or tag to the reader and detected in the input signal 2. The RFID reader according to this embodiment of the invention communicates with the tag according to the ECMA-340 13,56 MHz Near Field Communication NFC standard, which NFC Standard in-cooperates communication based on ISO/IEC 14.443 Type A and B and Felica, a company standard from company Sony. RFID reader furthermore comprises a transmitter, not shown in the figures, to emit a magnetic field via an antenna and to transmit data to one or more tags. Such a tag is for instance disclosed in document US 7,890,080 B2 which disclosure of the knowledge of a person skilled in the art is herewith incorporated into this disclosure.

When the RFID reader and the tag are within close proximity of each other, the RFID reader generated magnetic field is induced into the antenna of the tag and used to power the tag. The tag also has a transceiver to receive the signal from the RFID reader and to transmit a load modulated response back to RFID reader, which receives the response from the tag as load modulated analog input signal 2. RFID reader comprises the mixer stage 19 shown in figure 2 which comprises several elements of the mixer stage 1 shown in figure 1, which elements are numbered with the same reference numbers.

Mixer stage 19 of the receiver according to an embodiment of the invention comprises an in-phase mixer 3 that mixes the input signal 2 with an in-phase carrier frequency signal 4 provided by a carrier signal stage not shown in figure 1. The carrier signal stage provides the carrier signal which is in frequency and phase synchronized to the carrier signal received in the input signal of the receiver. Only this synchronized carrier signal enables a direct conversion receiver that uses its mixer stage to convert the received load modulated analogue input signal from the HF frequency area of e.g. 13,56MHz into the base band frequency area as shown in figure 4. After this conversion the load modulated input signal may be further processed in the base band frequency area by the receiver to output digital data detected in the input signal.

In-phase mixer 3 provides an in-phase component of a down-converted input signal 5 mixed with the clock signal 4 with a phase shift of 0° at output connection 6 of the in-phase mixer 3. In-phase mixer 3 furthermore provides an in-phase component of a down-converted input signal 8 mixed with the clock signal 4 with a phase shift of 180° at output connection 7 of the in-phase mixer 3. These in-phase down-converted input signals 5 and 8 comprise the received wanted information 27 of the load modulated input signal in the baseband frequency area and furthermore comprise unwanted harmonic multiples of the carrier signal as a result of the mixing. The received wanted information 27 is for instance within a bandwidth of about 2 MHz while the unwanted harmonic multiples are at multiples of the carrier signal so for instance at 27,12 MHz, 54,24 MHz and so on.

Mixer stage 19 furthermore comprises an in-phase amplifier 9 which is built as a differentiating amplifier to amplify the difference signal between the in-phase down- converted input signals 5 and 8. Amplified in-phase output signals of the in-phase amplifier 9 are provided on a negative and a positive output connection of in-phase amplifier 9 and form an in-phase output signal BBI of the mixer stage 1.

Mixer stage 19 furthermore comprises two parallel units 10 connected parallel to the in-phase amplifier 9. One of the parallel units 10 is connected to a positive input and a negative output of the in-phase amplifier 9 and another one of the parallel units 10 is connected to a negative input and a positive output of the in-phase amplifier 9. Each of the parallel units 10 comprises a capacity 11 and an ohmic resistance 12 connected parallel to each other. The capacity 11 is realized in the Pico Farad range to realize a low pass filter, which attenuates mixing harmonics as well as limiting the signal bandwidth to suppress noise and close by interferers. The impedance of unit 10 is realized parallel to the input and output of in-phase amplifier 9 and transforms the in-phase component from the current domain into the voltage domain.

The in-phase mixer 3 and the in-phase amplifier 9 and the two parallel units 10 form an in-phase processing stage for down-converting the in-phase component of the input signal 2. Mixer stage 19 furthermore comprises a quadrature-phase processing stage built identical like the in-phase processing stage to down-convert the quadrature-phase component of the input signal 2. A quadrature-phase mixer 13 mixes the input signal 2 with a quadrature-phase carrier frequency signal 14 with a phase shift of 90° and 270° and provides quadrature-phase components 15 and 16 of a down-converted input signal in the baseband frequency area with unwanted harmonic multiples. A quadrature-phase amplifier 17 amplifies the quadraturephase component 15 and 16 of the down-converted input signal. Amplified quadrature-phase output signals are provided on a negative and a positive output connection of quadraturephase amplifier 17 and form a quadrature-phase output signal BBQ of the mixer stage 1. Mixer stage 19 furthermore comprises a parallel in-phase mixer unit 20 connected parallel, but inverted to the output connections 6 and 7 of the in-phase mixer 3 to subtract the unwanted harmonic multiples. Inverted connected means that the in-phase component of a down-converted input signal 5 mixed with the carrier signal 4 with a phase shift of 0° is connected to output connection 7 of in-phase mixer 3 and that the in-phase component of a down-converted input signal 5 mixed with the carrier signal 4 with a phase shift of 180° is connected to output connection 6 of in-phase mixer 3. This inverse connection automatically leads to a subtraction of the output signals of both in-phase mixers 3 and 21. Parallel in-phase mixer unit 20 comprises a second in-phase mixer 21 with a serial filter capacity 22 connected at its output connections to block the baseband frequency area of the in-phase component of the down-converted input signal. To achieve that the serial filter capacity 22 is in the area of Pico Farad what enables that the unwanted first harmonic at 27,12 MHz and higher harmonics can pass through the serial filter capacity 22 while the baseband frequency area is blocked. The subtraction of the output signals of both in-phase mixers 3 and 21 enables that the wanted down-converted input signal in the baseband frequency area is amplified by in-phase amplifier 9 and results in a high quality in-phase output signal BBI with low harmonic content of the mixer stage 19.

Mixer stage 19 furthermore comprises a parallel quadrature-phase mixer unit 23 connected parallel, but inverted to the output connections of the quadrature-phase mixer 13 to subtract the unwanted harmonic multiples. The quadrature-phase mixer unit 23 comprises a second quadrature-phase mixer 24 with a serial filter capacity 22 connected at its output connections to block the baseband frequency area of the quadrature-phase component of the down-converted input signal. The serial filter capacities 22 of the in-phase mixer unit 20 and the quadrature-phase mixer unit 23 are realized with the same type and dimension. The same advantages are achieved for the quadrature-phase output signal BBQ of the mixer stage 19 as explained above for the in-phase output signal BBI of the mixer stage 19.

Figure 4 of the mixer 19 shows based on the example in figure 3 of the state of the art mixer 1 how the subtraction of the output signals of both in-phase mixers 3 and 21 and both quadrature-phase mixers 13 and 24 works. The upper diagram 25 in figure 4 is as the upper diagram in figure 3 and shows a frequency diagram of e.g. the in-phase carrier signal 4 with the frequency to of the clock signal LO of 13,56 MHz and sidebands with odd multiples of the clock signal LO. The middle diagram 26 in figure 4 is as the middle diagram in figure 3 and shows a frequency diagram of the load modulated analog input signal 2 with the received wanted information 27 around the carrier signal RF within a bandwidth of about 2 MHz. The lower diagram 29 in figure 4 shows a frequency diagram of the mixer output signal of the mixer 19 with the wanted information 27 in the baseband and with reduced amplitudes of the even mixing harmonics H2, H4. Because of the serial filter capacities 22, the in-phase mixer 21 and the quadrature-phase mixer 24 do see different impedances on their output compared to the in-phase mixer 3 and the quadrature-phase mixer 13. Therefore the amplitude of the output signals are different and therefore the subtraction does not completely eliminate the even mixing harmonics in the lower diagram 29. This would only be possible if the serial filter capacities 22 could be realized with an infinite capacity, what of course is only a fiction. Due to practical reasons in chip design it is possible to dimension the serial filter capacities in the PF area what leads to a cut in half of the amplitude of the even multiples in the diagram 29 compared to the diagram 28 of the state of the art mixer 1. This provides the advantage that in particular the first even multiple H2,BB of the mixer output signal in diagram 29 with its high amplitude as shown in diagram 28 is filtered/subtracted and cut in half and does not disturb the further processing of the wanted information 27. In another embodiment the serial filter capacities could be realized in the NF area what would lead to an even better reduction of the amplitude of the even multiples in the lower diagram 29.

In a preferred embodiment of the invention each of the in-phase correlators 3 and 21 and each of the quadrature-phase correlators 13 and 24 are from the same type and dimension. This is true and realized for all parallel built elements of the mixer stage 19. This ensures that the correlators have the same mixing functionality and for the same input signals lead to the same output signals what ensures that the subtraction of the unwanted harmonics works very accurate, what increases the quality of the signals BBI and BBQ.

In a preferred embodiment of the invention all the mixers 3, 13, 21 and 24 are realized as low ohmic passive mixers for the input signal in the current domain. This ensures a reliable realization of the invention. A low ohmic path is needed to ensure that the virtual ground is also provided at the input of the mixers. Otherwise we would see a voltage swing at the input of the mixers.

It is furthermore adventurous that the serial filter capacities 22 are realized as Metal on Metal capacitors or Metal -Isolator-Metal capacitors.

The inventive principle of the above explained mixer stage 19 may be used in all kind of different receivers and different applications outside of the RFID application area. Such applications could for instance be GSM, Bluetooth or LTE like many others.