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Title:
HARMONICS SUPPRESSION CIRCUIT FOR A SWITCH-MODE POWER AMPLIFIER
Document Type and Number:
WIPO Patent Application WO/2017/147955
Kind Code:
A1
Abstract:
Even harmonics are suppressed by a harmonics-reducing bias generator that drives bias voltages to cascode control transistors in series with driver transistors in a power amplifier. A first bias voltage is generated by mirroring pull-up currents in the power amplifier. A p-channel source transistor and a p-channel cascode current-mirror transistor also mirror the power amplifier pull-up current to a midpoint node. An n-channel sink transistor and an n-channel cascode current-mirror transistor mirror the pull-down current in the power amplifier to the midpoint node. An op amp compares the midpoint node to VDD/2, and drives the gate of a p-channel feedback transistor. Current from the p-channel feedback transistor flows through an n-channel cascode current-mirror transistor that generates a second bias voltage. The second bias voltage is adjusted until the midpoint node reaches VDD/2, causing the pull-up and pull-down currents in the power amplifier to better match, reducing even harmonics.

Inventors:
ZHENG SHIYUAN (CN)
WU ZHIWEI (CN)
Application Number:
CN2016/077388
Publication Date:
September 08, 2017
Filing Date:
March 25, 2016
Export Citation:
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Assignee:
HONG KONG APPLIED SCIENCE & TECH RES INST COMPANY LTD (CN)
International Classes:
H03F3/217
Domestic Patent References:
WO2013165653A12013-11-07
WO2013181114A12013-12-05
Foreign References:
EP2693634B12015-08-12
Attorney, Agent or Firm:
CHINA TRUER IP (Jiangxi Shiji Haoting Building Shennan Road South, Chegong Miao, Futian Distric, Shenzhen Guangdong 0, CN)
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