Title:
HDTV TRELLIS DECODER ARCHITECTURE
Document Type and Number:
WIPO Patent Application WO2003090451
Kind Code:
A3
Abstract:
A trellis decoding system (1) for use in processing a High Definition Television signal. The trellis decoding system includes a traceback unit (33) that identifies a sequence of antecedent trellis states in accordance with a state transition trellis. A branch metric computer (2) includes eight discrete subunits (3), one for each possible trellis state. Each subunit (3) generates two output bits (14, 15) indicative of the two trellis branches exiting the trellis state represente by that particular subunit (3). An add-compare-select unit (8) includes eight discrete subunits (23), each associated with a particular trellis state. Each subunit (23) includes as an input two bits (28, 29) received from the branch metric computer (2) and as an output two bits (6, 31). Bit 31 is chosen from 28 and 29. Bit 6 is chosen from the branch metric information (26, 27) input to each subunit (23). A traceback control and memory unit (33) includes an N to 1 multiplier (49) which receives as an input the output bits (6, 31) from the add-compare-select unit (8). The present system offers a hardware reduction from prior art.
Inventors:
MARKMAN IVONETE (US)
Application Number:
PCT/US2003/009862
Publication Date:
February 05, 2004
Filing Date:
April 01, 2003
Export Citation:
Assignee:
THOMSON LICENSING SA (FR)
MARKMAN IVONETE (US)
MARKMAN IVONETE (US)
International Classes:
H03M13/27; H03M13/41; H03M13/29; H04L5/12; (IPC1-7): H04L5/12
Foreign References:
| US5841478A | 1998-11-24 | |||
| US5923711A | 1999-07-13 | |||
| US20020001353A1 | 2002-01-03 |
Other References:
See also references of EP 1495572A4
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