SIDE THERMAL DISSIPATION LAYOUT

FIELD OF THE INVENTION

The present invention relates generally to removing heat from semiconductor device assemblies, and particularly to heat removal from photonic chips using combination of passive and thermoelectric cooling.

BACKGROUND OF THE INVENTION

Semiconductor device assemblies often employ means capable of removing heat from the assembled semiconductor devices. For example, U.S. Patent 6,094,919 describes a package for an integrated circuit (IC) comprises a lid attached to a base, with the IC being disposed in a space or cavity between the lid and the base. A thermoelectric module (TEM) having first and second primary surfaces is incorporated into a section of the lid. The first primary surface is thermally coupled to the IC such that application of power to the TEM causes heat to be transferred away from the IC.

As another example, U.S. Patent 8,063,298 describes a method of forming a thermoelectric device that may include providing a substrate having a surface, and thermally coupling a thermoelectric p-n couple to a first portion of the surface of a substrate. Moreover, the thermoelectric p-n couple may include a p-type thermoelectric element and an n-type thermoelectric element. In addition, a thermally conductive field layer may be formed on a second portion of the surface of the substrate adjacent the first portion of the surface of the substrate.

SUMMARY OF THE INVENTION

An embodiment of the present invention provides a semiconductor device assembly including a multi-layer printed circuit board (PCB), a thermoelectric cooler (TEC), a chip, and packaged integrated circuitry (IC). The multi-layer PCB includes a lateral heat conducting path formed in a recessed area of the PCB. The TEC and the chip are disposed on the PCB, side-by-side to one another over the lateral heat conducting path. The TEC is configured to evacuate heat from the chip via the lateral heat conducting path, and to dissipate the evacuated heat via a first end of a heat sink in thermal contact with the TEC. The packaged IC is disposed on an un-recessed area of the PCB, wherein the packaged IC is configured to dissipate heat via a second end of the heat sink that is in thermal contact with the packaged IC.

In some embodiments, the chip includes a silicon photonics (SiPh) chip. In some embodiments, the lateral heat conducting path includes heat conducting layers of the PCB, which are in thermal contact with an external surface of the heat conducting path via vertical heat conducting channels.

In an embodiment, the vertical heat conducting channels of the PCB are filled with thermally conductive material. In another embodiment, the lateral heat conducting path is thermally isolated from the IC.

In some embodiments, the heat sink is attached to a top side of the TEC and to a top side of the packaged IC, and the top sides of the TEC and the packaged IC are laterally separated by at least a lateral size of the chip.

In some embodiments, the assembly further includes a control circuit configured to adaptively control the TEC based on an operating power of the chip.

There is additionally provided, in accordance with an embodiment of the present invention, a manufacturing method, including forming in a recessed area of a multi-layer printed circuit board (PCB) a lateral heat conducting path. A thermoelectric cooler (TEC) and a chip are disposed on the PCB, side-by-side to one another on the lateral heat conducting path, wherein the TEC is configured to evacuate heat from the chip via the lateral heat conducting path, and to dissipate the evacuated heat via a first end of a heat sink in thermal contact with the TEC. Packaged integrated circuitry (IC) is disposed on an un-recessed area of the PCB , wherein the packaged IC is configured to dissipate heat via a second end of the heat sink that is in thermal contact with the packaged IC.

The present invention will be more fully understood from the following detailed description of the embodiments thereof, taken together with the drawings in which:

BRIEF DESCRIPTION OF THE DRAWINGS

Fig. 1 is a side view of a semiconductor device assembly comprising a thermoelectric cooler (TEC) and a silicon photonics (SiPh) chip disposed side-by-side over a lateral heat conducting path, in accordance with an embodiment of the present invention;

Fig. 2 is a flow chart that schematically illustrates a manufacturing method of the semiconductor device assembly of Fig. 1 , in accordance with an embodiment of the present invention;

Figs. 3A-3D are schematic sectional views showing successive stages in the manufacturing of the lateral heat conducting path over a recessed area of the printed circuit board (PCB) of Fig. 1, in accordance with an embodiment of the present invention; and Fig. 4 is schematic, pictorial isometric view of the lateral heat conducting path in the recessed area of the PCB of Fig. 1, in accordance with an embodiment of the present invention.

DETAILED DESCRIPTION OF EMBODIMENTS

OVERVIEW

Network devices, such as elements of network switches and network adapters, need to he robust in order to enable high data-rate communication traffic at sites having poor or no thermal management. At the same time, some semiconductor devices of such network elements, such as photonic devices (e.g., diode lasers, semiconductor optical amplifiers (SOA), and photodiodes) are considered sensitive to ambient temperature, in aspects of operational stability and reliability.

Conventionally, in order to remove heat from packaged semiconductor devices included in such devices, high air flow and bulky heat removal elements are required, such as an active thermoelectric cooler (TEC) that is often operated at a maximal power. Furthermore, achieving sufficient heat removal capacity may require a physically large configuration in which, for example, a passive cooling block is mounted back-to-back with the TEC, with the TEC placed back-to-back with the packaged semiconductor devices. Despite such efforts, photonic devices may occasionally experience high temperatures, for example, due to heat flowing from a nearby high-power electronic chip or due to fan failures.

Embodiments of the present invention that are described hereinafter provide improved techniques for heat removal from a semiconductor device assembly, such as a network element including temperature sensitive semiconductor devices (e.g., photonic devices). The disclosed techniques employ a compact configuration of a thermal solution having a dedicated lateral thermal heat removal solution from temperature sensitive devices, such as photonic devices. In some embodiments, the disclosed technique employs a multi-layer printed circuit board (PCB) comprising a lateral heat conducting path that is formed in a recessed area of the PCB. The heat conducting path includes heat conducting layers of the PCB that are in thermal contact with an external surface of the heat conducting path via vertical heat conducting channels. A TEC and a chip, such as a silicon photonics (SiPh) chip, are disposed side-by-side on the external surface of the lateral heat conducting path. The TEC is configured to evacuate heat from the SiPh chip via the lateral heat conducting path, and to dissipate the evacuated heat via a first end of a heat sink in thermal contact with the TEC. In addition, packaged integrated circuitry (IC) is disposed on an un-recessed area of the PCB, with the packaged IC configured to passively dissipate heat via a second end of the heat sink that is in thermal contact with the packaged IC.

In some embodiments, the disclosed lateral heat conducting path is thermally isolated from other elements of the assembly, such as from the IC, thereby ensuring a stable and predictable heat removal rate from the photonic devices regardless of a varying thermal output of other heat sources in the assembly, such as of the IC. In an embodiment, a control circuit, such as included in the assembly (e.g., in the packaged IC), adaptively controls the TEC based on the (known) operating power of the photonic devices (e.g., of a diode laser). This feature enables running the TEC at low power when possible, and at full power only when necessary.

The vertical heat conducting channels (e.g.,“vias”) in the recessed area of the PCB are formed as part of a manufacturing process of the PCB of the disclosed assembly. In an embodiment, the vertical channels are subsequently filled (e.g., by being plated) with thermally conductive material, such as metal. The heat conductive material may also cover the external surface of the heat conducting path.

In some embodiments, the heat conducting layers in the PCB are made extra thick to enable sufficient heat conducting capacity. In an embodiment, in order to achieve efficient heat flow from the bottom of the SiPh to existing heat conducting (e.g., metal) layers in the PCB, the vertical heat conducting channels may be filled by the same metal (e.g., copper). The heat conducting channels may be of one-dimensional and/or two-dimensional geometry, as described below.

In some embodiments, the TEC removes heat from semiconductor photonic devices that are disposed on the SiPh chip, such as diode lasers and semiconductor optical amplifiers (SOA). The TEC evacuates heat solely from these devices, enabling other electronics devices, such as a processor, to operate at elevated electronic chip temperatures that are otherwise prohibited due to the photonic devices. For example, the electronic chip, such as a processor, may be best operated at a temperature of 110 ^° C and, using the disclosed cooling techniques, the temperature of the photonic devices would be maintained up to 70°C. Without the disclosed lateral thermal solution, the operational temperature of the processor would have been restricted to sub 100 ^° C, causing sub-optimal utilization of the processor. Moreover, in case of a temperature deviation, due to, for example, fan failure, without the disclosed lateral thermal solution the photonic devices may experience adverse temperatures as high as 85°C. In that respect, the disclosed heat removal technique“guards” the sensitive devices from being subjected to adverse temperature spikes, thereby increasing the reliability of the devices.

The disclosed heat removal technique may also require less air cooling, which can reduce the form factor of the assembly, and the required electrical power for cooling. The disclosed technique may thus provide network devices capable of high data rate traffic at a reduced cost of a communication system.

HEAT REMOVAL FROM SILICON PHOTONICS CHIP USING A RECESSED SIDE-BY-

SIDE THERMAL DISSIPATION LAYOUT

Fig. 1 is a side view of a semiconductor device assembly 10 comprising a thermoelectric cooler (TEC) 30 and a silicon photonics (SiPh) chip 22 disposed side-by-side over a lateral heat conducting path 60, in accordance with an embodiment of the present invention. In the present example, assembly 10 is an opto-electronic transceiver used for realizing optical interconnects in datacenter environments.

Heat conducting path 60 is made in a recessed area 44 of a PCB 40 that is further processed to form path 60. Recessed area 44 comprises an external surface 61, with TEC 30 and SiPh chip 22 maintaining good thermal contact with path 60.

As seen, SiPh chip 22 includes one or more semiconductor devices 24. In the present example, a device 24A is a laser diode (e.g., a laser die), a device 24B is an SOA (e.g., an SOA die), and a device 24C is a photodiode. As seen, TEC 30 evacuates (55) heat from SiPh chip 22 generated by, or exposed to, photonic devices 24 via path 60. TEC 30 dissipates the evacuated heat into a heat sink 33.

Assembly 10 further comprises packaged integrated circuitry (IC) 28 disposed on an un-recessed area of PCB 40. Typically, packaged IC 28 includes driving and control electronics to drive and control photonic devices 24 disposed on SiPh chip 22. IC 28 generates heat that is evacuated directly by heat sink 33 that maintains a good thermal contact with the package of IC 28. Heat sink 33 is configured to maintain thermal equilibrium with the environment and to minimize any cross-thermal effects between heat dissipated from TEC 30 and heat dissipated from packaged IC 28. As seen, heat sink 33 has a U-shape, designed so as to enable optical access to the SiPh chip. For example, after the assembly of heat sink 33, a fiber array is aligned and attached on the SiPh chip.

Lateral heat conducting path 60 is thermally isolated from packaged IC 28. This isolation ensures a stable and predictable heat removal rate directly from photonic devices 24, and independently of heat generated by packaged IC 28. The side view shown in Fig. 1 is chosen purely for the sake of conceptual clarity. The design of partially recessed multilayer PCB 40, the layout of thermal channel 60, as well as the placement of TEC 30 and SiPh chip 22 may vary in alternative embodiments. Elements that are not mandatory for understanding of the disclosed techniques, such as electrical and optical interconnects, are omitted from the figure for simplicity of presentation.

Fig. 2 is a flow chart that schematically illustrates a manufacturing method of semiconductor device assembly 10 of Fig. 1, in accordance with an embodiment of the present invention. The process begins at a PCB manufacturing step 70, with the design and manufacturing of PCB 40, including, in some cases, forming extra-thick metal layers 50 that have the capacity to conduct heat at a sufficient rate. Layers 50 are further described in Fig. 3.

Next, at a heat conducting path formation step 72, PCB 40 is recessed and a path 60 is made in the recessed area of PCB 40, as also described in Fig. 3.

Next, photonic devices 24 and packaged IC 28 are assembled and interconnected on SiPh chip 22 and PCB 40, respectively, at an assembly step 74.

Next, SiPh chip 22 is attached on top of path 60 in a manufacturing process that ensures good thermal contact between the two, at SiPh attachment step 74.

At a mounting step 78, TEC 30 is attached on top of thermal path 60 in a process that ensures good thermal contact between the two. Finally, at a heat sink mounting step 80, heat sink 33 is put on top of TEC 30 and packaged IC 28, in a process that ensures good thermal contact between them and heat sink 33.

The flow chart of Fig. 2 is brought by way of example. Such an assembly process typically includes many steps and processes that are omitted for sake of clarity. For example, details, such as type of material used for attaching the elements, wire bonding, and optical interconnecting, are omitted.

Figs. 3A-3D are schematic sectional views showing successive stages in the manufacturing of the lateral heat conducting path over a recessed area of printed circuit board (PCB) 40 of Fig. 1, in accordance with an embodiment of the present invention. The manufacturing begins with accepting multilayer PCB 40, shown in side view in Fig. 3A, that comprises electrical insulating layers (48) and extra thick heat conducting layers (50). Extra thick layers 50, which may be as thick as 100 microns, are made of highly conductive thermal material, such as copper.

Fig. 3B shows PCB 40 after PCB 40 was recessed so as to enable thermal access to layers 50. The recess, in some cases, may be up to one millimeter deep. As seen in Fig. 3C, voids 56A are then formed in the recessed area, to expose, in part, side walls of layers 50. The voids may be formed in any one-dimensional pattern such as lines, or a two-dimensional pattern such as mesh of holes.

Finally, an overlayer of a thermally conductive material (e.g., copper) is disposed on the perforated recessed area, for example using metal plating. The result, seen in Fig. 3D, is heat conducting path 60 that comprises metal- filled holes 56B and external surface 61.

The schematic sectional views shown in Figs. 3A-D are brought by way of example. The composition and layer arrangement of PCB 40 may be different than that shown and described. Many details of processing steps, as well as some processing steps as a whole, are omitted for clarity. For example, possible steps of lithography to form masks, and surface polishing a deposited heat conductive overlayer to finish external surface 61, are not shown.

Fig. 4 is schematic, pictorial isometric view of the lateral heat conducting path in the recessed area of the PCB of Fig. 1, in accordance with an embodiment of the present invention. In the shown embodiments, filled voids 56B form a two-dimensional mesh of metal-filled circular holes 62. Filled holes 62 form thermal channels to heat conducting layers 50 and, as a whole, lateral heat conducting path 60 serves as a foundation for mounting (i.e., on external surface 61 of path 60) SiPh chip 22 and TEC 30.

The isometric view shown in Fig. 4 is brought by way of example. The geometry of voids 56 may differ and be any designed one-dimensional and/or two-dimensional pattern, as described above.

Although the embodiments described herein mainly address thermal solution for circuitries transmitting and/or receiving optical, as well as electrical signals, at high rates for communication, such as in pluggable transceiver modules, the methods and systems described herein can also be used in other applications, such as in mid-board optics modules, for example, along COBO (consortium for on-board optics) guidelines for key critical component for co-packaging. The disclosed technique may thus be applied to a photonic transceiver module that instead of a pluggable, is hosted in a specialized assembly very close to a high power switching electronic chip.

It will thus be appreciated that the embodiments described above are cited by way of example, and that the present invention is not limited to what has been particularly shown and described hereinabove. Rather, the scope of the present invention includes both combinations and sub-combinations of the various features described hereinabove, as well as variations and modifications thereof which would occur to persons skilled in the art upon reading the foregoing description and which are not disclosed in the prior art. Documents incorporated by reference in the present patent application are to be considered an integral part of the application except that to the extent any terms are defined in these incorporated documents in a manner that conflicts with the definitions made explicitly or implicitly in the present specification, only the definitions in the present specification should be considered.