Title:
HIGH-BANDWIDTH DDR DUAL-IN-LINE MEMORY MODULE, AND MEMORY SYSTEM AND OPERATION METHOD THEREFOR
Document Type and Number:
WIPO Patent Application WO/2024/031798
Kind Code:
A9
Abstract:
Disclosed in the present invention are a high-bandwidth DDR dual-in-line memory module, and a memory system and an operation method therefor. The high-bandwidth DDR dual-in-line memory module comprises a first sub-channel, a second sub-channel, a frequency-division clock latch driver and a combined data buffer, wherein each sub-channel comprises a first pseudo channel and a second pseudo channel, and each pseudo channel comprises a plurality of DRAM chip particles; the frequency-division clock latch driver is used for determining an instruction mode in response to an instruction, which is sent by a host, and sending the instruction to the first pseudo channel and/or the second pseudo channel according to the instruction mode; and the combined data buffer is used for interweaving data of the first pseudo channel with data of the second pseudo channel. By means of the present invention, it is not necessary to change an original instruction sending mode, and a frequency-division clock latch driver determines different instruction modes in response to received instructions, and simultaneously or separately sends the instructions to a plurality of pseudo channels, thereby reading data more quickly and more effectively.
Inventors:
ZHANG LIANG (CN)
ZHANG JIAYUN (CN)
SHOU JIECHEN (CN)
XU CHUANHAO (CN)
HUANG MING (CN)
ZHANG JIAYUN (CN)
SHOU JIECHEN (CN)
XU CHUANHAO (CN)
HUANG MING (CN)
Application Number:
PCT/CN2022/121590
Publication Date:
April 11, 2024
Filing Date:
September 27, 2022
Export Citation:
Assignee:
INNOSILICON MICROELECTRONICS ZHUHAI CO LTD (CN)
International Classes:
G11C11/4076; G11C7/10; G11C7/22
Attorney, Agent or Firm:
SHANGHAI BILIPAT INTELLECTUAL PROPERTY AGENCY LTD. (CN)
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