Title:
HIGH BANDWIDTH DIGITAL PHASE-LOCKED LOOP USING POSITIVE EDGE AND FALLING EDGE OF SIGNAL
Document Type and Number:
WIPO Patent Application WO/2017/099368
Kind Code:
A1
Abstract:
Disclosed is a high bandwidth digital phase-locked loop using a positive edge and a falling edge of a signal. The disclosed digital phase-locked loop controls a frequency of a digital voltage control oscillator by comparing both a phase difference between a reference signal and a positive edge of a feedback signal and a phase difference between the reference signal and a falling edge.
Inventors:
YOO CHANG SIK (KR)
Application Number:
PCT/KR2016/012911
Publication Date:
June 15, 2017
Filing Date:
November 10, 2016
Export Citation:
Assignee:
INDUSTRY-UNIV COOP FOUND HANYANG UNIV (KR)
International Classes:
H03L7/099; G04F10/00; H03L7/089; H03L7/093
Foreign References:
KR20110070719A | 2011-06-24 | |||
US20120161831A1 | 2012-06-28 | |||
KR20150069497A | 2015-06-23 | |||
KR20090033783A | 2009-04-06 | |||
KR20100062893A | 2010-06-10 |
Attorney, Agent or Firm:
SONG, In-Ho (KR)
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