Technical Field

[0001 ] Embodiments of the invention are in the field of semiconductor devices and, in particular, high density memory.

Background

[0002] Many electronic devices use dynamic random-access memory (DRAM) integrated circuits for the temporary storage of programs and/or data. In DRAM, each bit of data is stored in a separate capacitor within the integrated circuit. The capacitor can be in, for example, either of two states: charged or discharged. These two states represent two values of a bit, commonly referred to as "0" and "1 ". Since the sensing circuitry in a DRAM integrated circuit needs to determine whether the capacitor is charged or discharged, the DRAM cell is often designed such that overall capacitance and capacitance variation are minimized while the resistance of the interconnect that connects access transistors to the storage capacitors is of secondary importance.

Brief Description of the Drawings

[0003] Features and advantages of embodiments of the present invention will become apparent from the appended claims, the following detailed description of one or more example embodiments, and the corresponding figures. Where considered appropriate, reference labels have been repeated among the figures to indicate corresponding or analogous elements.

Figure 1 includes a top view of a memory array in an embodiment of the invention;

Figure 2 includes a cross sectional view of the memory array of Figure 1 ;

Figures 3, 4, 5, 6, 7, 8, 9, 10, 1 1 , 12, 13, 14, and 15 depict varying stages of a method of producing the memory array of Figure 1 ; and

Figure 16 includes a system including the memory array of Figure 1 . Detailed Description

[0004] Reference will now be made to the drawings wherein like structures may be provided with like suffix reference designations. In order to show the structures of various embodiments more clearly, the drawings included herein are diagrammatic representations of semiconductor/circuit structures. Thus, the actual appearance of the fabricated integrated circuit structures, for example in a photomicrograph, may appear different while still incorporating the claimed structures of the illustrated embodiments. Moreover, the drawings may only show the structures useful to understand the illustrated embodiments. Additional structures known in the art may not have been included to maintain the clarity of the drawings. For example, not every layer of a semiconductor device is necessarily shown. "An embodiment", "various embodiments" and the like indicate embodiment(s) so described may include particular features, structures, or characteristics, but not every embodiment necessarily includes the particular features, structures, or characteristics. Some embodiments may have some, all, or none of the features described for other embodiments. "First", "second", "third" and the like describe a common object and indicate different instances of like objects are being referred to. Such adjectives do not imply objects so described must be in a given sequence, either temporally, spatially, in ranking, or in any other manner. "Connected" may indicate elements are in direct physical or electrical contact with each other and "coupled" may indicate elements co-operate or interact with each other, but they may or may not be in direct physical or electrical contact.

[0005] The above mentioned DRAM faces severe scaling issues. As the size of the storage capacitors continues to shrink, less and less charge can be stored in the storage capacitors. Storage capacitors may become so small that sensing circuitry will no longer be able to accurately determine the state of the storage capacitor (e.g. charged vs. discharged). For this reason other types of memory may be used, such as Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM).

[0006] In STT-MRAM each bit of data is stored in a separate magnetic tunnel junction (MTJ), which is a magnetic element comprised of two magnetic layers separated by a thin insulating layer. One of the magnetic layers is called the reference layer (RL), and it provides a stable reference magnetic orientation. The bit is stored in the second magnetic layer, which is called the free layer (FL), and the orientation of the magnetic moment of the free layer can be, for example, in either of two states: parallel to the reference layer or anti-parallel to the reference layer.

Because of the tunneling magnetoresistance (TMR) effect, the electrical resistance of the anti-parallel state is significantly higher compared to the parallel state.

[0007] To write information in a STT-MRAM device, the spin transfer torque effect is used to switch the free layer from the parallel to anti-parallel state and vice versa. The passing of current through the MTJ produces spin polarized current, which results in a torque being applied to the magnetization of the free layer. When the spin polarized current is sufficiently strong, enough torque is applied to the free layer to cause its magnetic orientation to change, thus allowing for bits to be written. To read the stored bit, the sensing circuitry measures the resistance of the MTJ.

[0008] Since the sensing circuitry needs to determine whether the MTJ is in the low resistance (e.g. parallel) state or in the high resistance state (e.g. anti-parallel) with an acceptable signal-to- noise ratio, the STT-MRAM cell needs to be designed such that overall electrical resistance and resistance variation of the cell and related interconnects are minimized and the capacitance of the cell is of secondary importance. Note that these STT-MRAM cell design requirements are the opposite of that for DRAM, as described above, so using prior art DRAM cell layouts does not result in optimal STT-MRAM performance.

[0009] Embodiments address the need for lower interconnect resistance. Such embodiments include a high density bit cell layout and a fabrication method for STT- MRAM applications. An embodiment of the high density STT-MRAM memory cell is illustrated in Figures 1 and 2. The embodiment of Figure 1 includes: (a) tilted transistor fins, (b) parallelogram-shaped diffusion contacts, (c) "MTJ pillar vias" (MPVs) that connect the bottom of the MTJs to the top of drain-side contacts (e.g., above mentioned parallelogram-shaped diffusion contacts), and/or (d) MPVs that are self-aligned to one side of an adjacent source line. Embodiments described herein may include some, all, or none of elements (a)-(d). [0010] For embodiments with self-aligned MPVs, self-aligning the MPVs to one side of the adjacent source line allows for the source lines to be relatively wider than source lines in conventional DRAM and conventional STT-MRAM. The use of wider source lines lowers the overall resistance of the interconnects between access transistors and MTJs. The lowered resistance results in an improved signal-to-noise ratio for MTJ read operations and lowered transistor drive current requirements for MTJ write operations. Also, self-aligning the MPVs to one side of the adjacent source line allows for the bit cell dimension (which is perpendicular to the source line direction) to be compressed, which reduces the overall bit cell area. In other words, if the MPV is not self-aligned space may need to be left between the MPV and the adjacent source line to allow for overlay error. To make room for the overlay error one may (1 ) increase the cell dimensions, or (2) decrease the width of the source line, which increases the source line resistance.

[001 1 ] Figures 1 and 2 are now described. Generally, the embodiment shown includes tilted transistor fins, parallelogram-shaped diffusion contacts, wide source lines, source line vias that connect the source lines to the underlying source-side parallelogram-shaped diffusion contacts, and MPVs that connect the bottom of the MTJs to the top of the drain-side parallelogram-shaped diffusion contacts and that are self-aligned to one side of the adjacent source line.

[0012] In an embodiment, vertical sidewalls of the parallelogram contacts may be self-aligned to a polysilicon gate of a transistor. For example, wall 163 may be self- aligned to polysilicon 194. In embodiments, multiple walls of a contact may be self- aligned to multiple gates. For example, wall 163 may be self-aligned to polysilicon 194 and wall 164 may be self-aligned to an additional polysilicon gate.

[0013] Specifically, STT-MRAM array 100 of Figures 1 and 2 includes a first semiconductor fin 101 parallel to a second semiconductor fin 102. A first source line 1 1 1 is oblique to the first and second fins. In other words, line 1 1 1 is not parallel or orthogonal to the first and second fins. A first contact 121 couples a first drain node 131 of the first fin to a first MTJ 141 and a second contact 122 coupling a second drain node 132 of the second fin to a second MTJ 142. A first vertical axis 151 intersects the first fin and the first source line 1 1 1 and a second vertical axis 152 intersects the second fin and the first source line 1 1 1 . The first contact 121 includes sidewalls 161 , 162 parallel to the first fin and additional sidewalls 163, 164

orthogonal to the first source line and the second contact 122 includes sidewalls 165, 166 parallel to the second fin and additional sidewalls 167, 168 orthogonal to the first source line. Regarding the sidewalls for either of contacts 121 , 123, such sidewalls may collectively form a parallelogram.

[0014] A first via 171 couples the first MTJ 141 to the first contact 121 and a second via 172 couples the second MTJ 142 to the second contact 122. The first via 171 includes a sidewall 173 parallel to a sidewall of the first source line 1 1 1 and the second via 172 includes a sidewall 174 parallel to a sidewall of the first source line 1 1 1 . Such vias may be considered self-aligned to the first source line. In the embodiment of Figure 1 , the first and second vias 171 , 172 are adjacent opposing sidewalls of the first source line.

[0015] First vertical axis 151 intersects the first via 171 and second vertical axis 152 intersects the second via 172. A first horizontal axis 153, orthogonal to the first and second vertical axes, intersects the first and second fins 101 , 102. In an embodiment, axis 153 intersects the first and second drain nodes 131 , 132.

[0016] Array 100 includes a first source node 133 (on the first fin 101 ) that corresponds to the first drain node 131 and a second source node 134 (on the second fin 102) that corresponds to the second drain node 132. A second horizontal axis 154, parallel to the first horizontal axis 153, intersects the first source node 133 but not the second source node 134.

[0017] A third semiconductor fin 103 is parallel to the second semiconductor fin 102 (i.e., parallel encompasses collinear arrangements). A second source line 1 12 is oblique to the third fin 103. A third contact 123 couples a third drain node 135 of the third fin to a third MTJ (not shown). The second horizontal axis 154 intersects the third drain node 135.

[0018] A third vertical axis 155 (shown going "into" the page of Figure 1 ) intersects the third fin 103, the second source line 1 12, and a third via 175 that couples the third MTJ to the third contact 123. [0019] The third fin 103 is collinear with the second fin 102 and separate from the second fin due to polysilicon 194. Polysilicon 194 forms the gate contact for the gate between drain node 131 and source node 133.

[0020] An additional drain node 136 is on the first fin 101 . An additional contact 124 couples the additional drain node 136 to an additional MTJ (not shown). The first source node 133 and drain node 131 are included in a first access transistor (with polysilicon 194 as a gate contact for a channel of the first access transistor) for accessing the first MTJ and the first source node is included in an additional access transistor (along with drain node 136 and polysilicon 195 as a gate contact for a channel of the additional access transistor) for accessing the additional MTJ.

[0021 ] Figure 3, 4, 5, 6, 7, 8, 9, 10, 1 1 , 12, 13, 14, and 15 depict varying stages of a method of producing the memory array 100 of Figures 1 and 2.

[0022] Figure 3 depicts substrate 180 with completed transistor fins 101 , 102 (and other fins that are not labeled for purposes of clarity) that are tilted relative to the directions of the transistor gates and source line interconnect. The tilted transistor fins 101 , 102 and parallelogram-shaped diffusion contacts 121 , 122 are fabricated using conventional methods and techniques.

[0023] In Figure 4 an etch stop material 181 is deposited onto the wafer surface, followed by a dielectric layer 182, and a metallization hardmask layer 183. The etch stop material may consist of, for example, silicon nitride, silicon carbide, or silicon oxynitride. The dielectric material may consist of, for example, a silicon dioxide, silicon nitride, fluorinated silicon oxide (SiOF), borophosphosilicate glass (BPSG), or a low k dielectric (e.g., k<3) such as carbon-doped oxide (CDO). The metallization hardmask layer may consist of, for example, silicon nitride, titanium nitride, tantalum nitride, titanium dioxide, or doped or undoped polysilicon, or a combination of these films.

[0024] In Figure 5 photoresist 184 is applied to the wafer surface and patterned. After patterning there are trenches 185 in the photoresist layer where source lines are desired. The photoresist layer may consist not only of photoresist material, but also may include other patterning materials such as, for example, anti-reflective coatings (ARCs) and gap-fill and planarizing materials that are applied using methods and techniques that are well-known in the art.

[0025] In Figure 6 anisotropic dry etch processes are then used to transfer the source line resist pattern into the metallization hardmask layer and the dielectric layer. Afterwards, any remaining resist layer is removed using a plasma ash process.

[0026] In Figure 7 photoresist 185 is applied to the wafer surface and patterned. After patterning there are openings 186 in the photoresist layer where source line vias are desired. In Figure 7 "source line via" is written but this is just showing where the via will be formed, as is the case where "source line" is written indicating a source line will eventually be located at that location. The photoresist layer may consist not only of photoresist material, but also may include other patterning materials such as, for example, ARCs and gap-fill and planarizing materials that are applied using methods and techniques that are well-known in the art. Anisotropic dry etch processes are then used to transfer the resist pattern into the dielectric layer and the edge stop layer. Any remaining resist layer is then removed using a plasma ash process (not shown).

[0027] In Figure 8 a conductive metal 187 such as, for example, copper, tungsten or cobalt is deposited onto then entire wafer surface, filling into the source line trenches and source line via openings. Various barrier or adhesion films may be present at the interface between the conductive metal and the surrounding dielectric, such as, for example, titanium, tantalum, titanium nitride, tantalum nitride, ruthenium, titanium-zirconium nitride, cobalt, etc., and the like.

[0028] In Figure 9 the conductive metal overburden is etched back using wet etch, dry etch and/or CMP processes. The etchback process stops on the metallization hard mask material 183 and the source line conductive metal is etched back in the hardmask and dielectric openings such that its top surface is recessed below the top surface of the dielectric layer 182 when the etchback process is completed. [0029] In Figure 10 a source line passivation film 188 is deposited onto the wafer surface using CVD techniques. Suitable source line passivation materials include, for example, silicon nitride, silicon carbide, and carbon-doped silicon nitride.

[0030] The source line passivation overburden and metallization hard mask are removed using CMP and dry and wet etch processes, stopping on the dielectric material 182. Afterwards, in Figure 1 1 the wafer surface is covered with an "MPV polish stop" film 189, followed by an "MPV hardmask material 190. Suitable materials for the MPV polish stop film include, for example, silicon nitride, silicon carbide, or carbon-doped silicon nitride. Suitable MPV hardmask material may include, for example, titanium nitride, tantalum nitride, titanium dioxide, or doped or undoped polysilicon, or a combination of these films.

[0031 ] Photoresist 191 is then applied to the wafer surface and patterned. After patterning there are openings 192 in the photoresist layer where MPVs are desired. The photoresist layer may consist not only of photoresist material, but also may include other patterning materials such as, for example, ARCs and gap-fill and planarizing materials that are applied using methods and techniques that are well- known in the art. Figure 12 includes anisotropic dry etch processes used to transfer the resist pattern into the MPV hardmask layer 190, the MPV polish stop film 189, the dielectric layer 182, and the etch stop layer 180 to form holes 192 where MPVs are desired (Figure 12). In an embodiment such as Figure 12 the MPVs are self- aligned to the edges of the source lines 1 1 1 , 1 12. In an embodiment, the source line passivation material 188 is thick enough so that enough material remains after the anisotropic dry etch processes are completed to prevent an electrical short circuit between the MPV and the adjacent source line.

[0032] Any remaining resist layer 191 is removed using a plasma ash process step. In Figure 13 an MPV spacer film 193 is deposited onto the wafer surface using CVD techniques. Suitable MPV spacer materials include, for example, silicon nitride, silicon carbide and carbon-doped silicon nitride.

[0033] An anisotropic dry etch process is used to remove the MPV spacer material from all of the horizontal surfaces of the wafer while leaving the spacer material on the vertical sidewalls. In Figure 14 the remaining MPV hardmask material is removed using wet etch or dry etch techniques.

[0034] A conductive metal 193 such as, for example, copper, tungsten or cobalt is deposited onto the entire wafer surface, filling into the MPV gaps 192. Various barrier or adhesion films may be present at the interface between the conductive metal and the MPV spacer, such as, for example, titanium, tantalum, titanium nitride, tantalum nitride, ruthenium, titanium- zirconium nitride, cobalt, and the like. In Figure 15 the conductive metal overburden is removed using wet etch, dry etch and/or CMP processes stopping on the MPV polish stop material to yield MPVs 171 , 172.

[0035] MTJ devices 141 , 142 are then fabricated on top of the MPVs 171 , 172, and then subsequent interconnect layer(s) are fabricated on top of the MTJ devices, as shown in Figure 2.

[0036] Access transistors including, for example, nodes 131 , 133 may be FinFETs. A FinFET is a transistor built around a thin strip of semiconductor material (referred to as the "fin"). The transistor includes the standard field effect transistor (FET) nodes/components: a gate, a gate dielectric, a source region, and a drain region. The conductive channel of the device resides on the outer sides of the fin beneath the gate dielectric. Specifically, current runs along both "sidewalls" of the fin as well as along the top side of the fin. Because the conductive channel essentially resides along the three different outer, planar regions of the fin, such a FinFET is typically referred to as a "tri-gate" FinFET. Other types of FinFETs exist (such as "double- gate" FinFETs in which the conductive channel principally resides only along both sidewalls of the fin and not along the top side of the fin).

[0037] Various embodiments disclosed herein have addressed MTJs (which includes MTJs and perpendicular MTJs (pMTJ)). As shown to various extents in Figures 1 and 2, any such pMTJ or MTJ may be used in a memory cell by coupling one portion or node of the MTJ/pMTJ stack (e.g., a top electrode for the MTJ) to a bit-line and another node of the MTJ/pMTJ stack (e.g., a bottom electrode for the MTJ) to a source or drain node of a switching device, such as a selection transistor. The other of the source and drain node of the selection transistor may be coupled to a source line of the memory cell. The gate of the selection transistor may couple to a word-line. Such a STT memory cell may utilize TMR of the MTJ/pMTJ to store memory states. The STT memory cell may couple to a sense amplifier. A plurality of the STT memory bit cells may be operably connected to one another to form a memory array (such as array 100 of Figure 1 ), wherein the memory array can be incorporated into a non-volatile memory device. It is to be understood that the selection transistor may be connected to the top electrode or the bottom electrode of a MTJ/pMTJ stack.

[0038] Figure 16 includes a system that may include any of the above described embodiments. Figure 16 includes a block diagram of a system embodiment 1000 in accordance with an embodiment of the present invention. System 1000 may include hundreds or thousands of the above described memory cells and be critical to memory functions in system 1000. System 1000 may be included in, for example, a mobile computing node such as a cellular phone, smartphone, tablet, Ultrabook®, notebook, laptop, personal digital assistant, and mobile processor based platform. The stability and power efficiency of such memory cells accumulates when the memory cells are deployed in mass and provides significant performance

advantages (e.g., longer battery life, longer memory state storage in a broader range of operating temperatures) to such computing nodes.

[0039] Shown is a multiprocessor system 1000 that includes a first processing element 1070 and a second processing element 1080. While two processing elements 1070 and 1080 are shown, it is to be understood that an embodiment of system 1000 may also include only one such processing element. System 1000 is illustrated as a point-to-point interconnect system, wherein the first processing element 1070 and second processing element 1080 are coupled via a point-to-point interconnect 1050. It should be understood that any or all of the interconnects illustrated may be implemented as a multi-drop bus rather than point-to-point interconnect. As shown, each of processing elements 1070 and 1080 may be multicore processors, including first and second processor cores (i.e., processor cores 1074a and 1074b and processor cores 1084a and 1084b). Such cores 1074, 1074b, 1084a, 1084b may be configured to execute instruction code. [0040] Each processing element 1070, 1080 may include at least one shared cache or memory unit which may include pMTJs and/ or MTJs described herein (e.g., MTJs may be in embedded memory). The shared cache may store data (e.g., instructions) that are utilized by one or more components of the processor, such as the cores 1074a, 1074b and 1084a, 1084b, respectively. For example, the shared cache may locally cache data stored in a memory 1032, 1034 for faster access by components of the processor. In one or more embodiments, the shared cache may include one or more mid-level caches, such as level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache, a last level cache (LLC), and/or combinations thereof.

[0041 ] While shown with only two processing elements 1070, 1080, it is to be understood that the scope of the present invention is not so limited. In other embodiments, one or more additional processing elements may be present in a given processor. Alternatively, one or more of processing elements 1070, 1080 may be an element other than a processor, such as an accelerator or a field

programmable gate array. For example, additional processing element(s) may include additional processors(s) that are the same as a first processor 1070, additional processor(s) that are heterogeneous or asymmetric to first processor 1070, accelerators (such as, e.g., graphics accelerators or digital signal processing (DSP) units), field programmable gate arrays, or any other processing element. There can be a variety of differences between the processing elements 1070, 1080 in terms of a spectrum of metrics of merit including architectural, microarchitectural, thermal, power consumption characteristics, and the like. These differences may effectively manifest themselves as asymmetry and heterogeneity amongst the processing elements 1070, 1080. For at least one embodiment, the various processing elements 1070, 1080 may reside in the same die package.

[0042] First processing element 1070 may further include memory controller logic (MC) 1072 and point-to-point (P-P) interfaces 1076 and 1078. Similarly, second processing element 1080 may include a MC 1082 and P-P interfaces 1086 and 1088. MCs 1072 and 1082 couple the processors to respective memories, namely a memory 1032 and a memory 1034, which may be portions of main memory locally attached to the respective processors. Memory 1032, 1024 may include MTJs/pMTJs described herein. While MC logic 1072 and 1082 is illustrated as integrated into the processing elements 1070, 1080, for alternative embodiments the MC logic may be discreet logic outside the processing elements 1070, 1080 rather than integrated therein.

[0043] First processing element 1070 and second processing element 1080 may be coupled to an I/O subsystem 1090 via P-P interfaces 1076, 1086 via P-P

interconnects 1062, 10104, respectively. As shown, I/O subsystem 1090 includes P- P interfaces 1094 and 1098. Furthermore, I/O subsystem 1090 includes an interface 1092 to couple I/O subsystem 1090 with a high performance graphics engine 1038. In one embodiment, a bus may be used to couple graphics engine 1038 to I/O subsystem 1090. Alternately, a point-to-point interconnect 1039 may couple these components.

[0044] In turn, I/O subsystem 1090 may be coupled to a first bus 101 10 via an interface 1096. In one embodiment, first bus 101 10 may be a Peripheral Component Interconnect (PCI) bus, or a bus such as a PCI Express bus or another third generation I/O interconnect bus, although the scope of the present invention is not so limited.

[0045] As shown, various I/O devices 1014, 1024 may be coupled to first bus 101 10, along with a bus bridge 1018 which may couple first bus 101 10 to a second bus 1020. In one embodiment, second bus 1020 may be a low pin count (LPC) bus. Various devices may be coupled to second bus 1020 including, for example, a keyboard/mouse 1022, communication device(s) 1026 (which may in turn be in communication with a computer network), and a data storage unit 1028 such as a disk drive or other mass storage device which may include code 1030, in one embodiment. The code 1030 may include instructions for performing embodiments of one or more of the methods described above. Further, an audio I/O 1024 may be coupled to second bus 1020.

[0046] Note that other embodiments are contemplated. For example, instead of the point-to-point architecture shown, a system may implement a multi-drop bus or another such communication topology. Also, the elements of Figure 16 may alternatively be partitioned using more or fewer integrated chips than shown in the Figure 16. For example, a field programmable gate array may share a single wafer with a processor element and memory including MTJs described herein.

[0047] Various embodiments addressed herein include a semiconductive substrate. Such a substrate may be a bulk semiconductive material this is part of a wafer. In an embodiment, the semiconductive substrate is a bulk semiconductive material as part of a chip that has been singulated from a wafer. In an embodiment, the

semiconductive substrate is a semiconductive material that is formed above an insulator such as a semiconductor on insulator (SOI) substrate. In an embodiment, the semiconductive substrate is a prominent structure such as a fin that extends above a bulk semiconductive material.

[0048] Also, please note the shapes of the various elements in the figures are idealized and on an actual wafer the real features may differ from the idealized renderings of the figures. For example, in Figure 1 the parallelogram shaped diffusion contacts have sharp points but in actual practice the points may be rounded due to photolithography/resist and etch processing resolution limits. Another example is that the cross-section process flow figures show the MTJs as rectangles, but on actual wafers the top width of an MTJ may be somewhat narrower than the bottom width because the MTJ etch may not be perfectly anisotropic.

[0049] The following examples pertain to further embodiments.

[0050] Example 1 includes an apparatus comprising: a first semiconductor fin parallel to a second semiconductor fin; a first source line oblique to the first and second fins; a first contact coupling a first drain node of the first fin to a first magnetic tunnel junction (MTJ) and a second contact coupling a second drain node of the second fin to a second MTJ; wherein (a) a first vertical axis intersects the first fin and the first source line and a second vertical axis intersects the second fin and the first source line; and (b) the first contact includes sidewalls parallel to the first fin and additional sidewalls orthogonal to the first source line and the second contact includes sidewalls parallel to the second fin and additional sidewalls orthogonal to the first source line. [0051 ] By saying first contact includes sidewalls parallel to the first fin and additional sidewalls orthogonal to the first source line a person of ordinary skill in the art will understand this to mean the first contact includes sidewalls substantially or generally parallel (but not necessarily 100% parallel) to the first fin and additional sidewalls substantially or general orthogonal (but not necessarily 100% orthogonal) to the first source line.

[0052] In example 2 the subject matter of the Example 1 can optionally include wherein the first and second contacts each include a cross-section with sidewalls that form a parallelogram.

[0053] In example 3 the subject matter of the Examples 1 -2 can optionally include a first via coupling the first MTJ to the first contact and a second via coupling the second MTJ to the second contact.

[0054] In example 4 the subject matter of the Examples 1 -3 can optionally include wherein the first via includes a sidewall parallel to a sidewall of the first source line and the second via includes a sidewall parallel to another sidewall of the first source line.

[0055] In example 5 the subject matter of the Examples 1 -4 can optionally include wherein the first via is self-aligned to the first source line and the second via is self- aligned to the first source line.

[0056] In another embodiment, the first contact includes a sidewall orthogonal to the first source line and self-aligned to a first gate of the first fin.

[0057] In another embodiment, the first contact includes sidewalls orthogonal to the first source line and self-aligned to a first gate of the first fin and a second gate of the second fin. In such an embodiment the first and second gates may include polysilicon.

[0058] In another embodiment, the first contact includes sidewalls orthogonal to the first source line and self-aligned to a first gate of the first fin and a second column that includes a second gate of the second fin. In such an embodiment second column may include polysilicon. [0059] In another embodiment, the additional sidewalls of the first contact are parallel to a side wall of a first gate of the first fin and a side wall of a second gate of the second fin. In such an embodiment the additional sidewalls of the first contact are self aligned to the side wall of the first gate of the first fin and the side wall of the second gate of the second fin.

[0060] Thus, in an embodiment edges of parallelogram-shaped diffusion contacts 121 , 122 are self-aligned to one or more adjacent polysilicon gates (e.g., 194).

Spaces between two polysilicon gates become diffusion contacts or may instead include dielectric. For the sidewalls parallel to tilted transistor fins, those walls may be separated from each other by dielectric. Dielectric between parallelogram diffusion contacts in the vertical direction is covered by photoresist during contact formation process. Area between polysilicon gates that is not covered by photoresist will be etched so diffusion contacts may be formed.

[0061 ] For example, wall 163 may be self-aligned to polysilicon 194. In

embodiments, multiple walls of a contact may be self-aligned to multiple gates. For example, wall 163 may be self-aligned to polysilicon 194 and wall 164 may be self- aligned to an additional polysilicon gate.

[0062] In example 6 the subject matter of the Examples 1 -5 can optionally include wherein the first and second vias are adjacent opposing sidewalls of the first source line.

[0063] In example 7 the subject matter of the Examples 1 -6 can optionally include wherein the first vertical axis intersects the first via and the second vertical axis intersects the second via.

[0064] In example 8 the subject matter of the Examples 1 -7 can optionally include wherein a first horizontal axis, orthogonal to the first and second vertical axes, intersects the first and second fins.

[0065] In example 9 the subject matter of the Examples 1 -8 can optionally include wherein a first horizontal axis, orthogonal to the first and second vertical axes, intersects the first and second drain nodes. [0066] In example 10 the subject matter of the Examples 1 -9 can optionally include a first source node on the first fin that corresponds to the first drain node and a second source node on the second fin that corresponds to the second drain node; wherein a second horizontal axis, parallel to the first horizontal axis, intersects the first source node but not the second source node.

[0067] In example 1 1 the subject matter of the Examples 1 -10 can optionally include a third semiconductor fin parallel to the second semiconductor fin; a second source line oblique to the third fin; and a third contact coupling a third drain node of the third fin to a third MTJ; wherein the second horizontal axis intersects the third drain node.

[0068] In example 12 the subject matter of the Examples 1 -1 1 can optionally include wherein a third vertical axis intersects the third fin, the second source line, and a third via that couples the third MTJ to the third contact.

[0069] In example 13 the subject matter of the Examples 1 -12 can optionally include wherein the third fin is collinear with the second fin and separate from the second fin.

[0070] In example 14 the subject matter of the Examples 1 -13 can optionally include an additional drain node on the first fin; an additional MTJ; and an additional contact coupling the additional drain node to the additional MTJ; wherein the first source node is included in a first access transistor for accessing the first MTJ and the first source node is included in an additional access transistor for accessing the additional MTJ.

[0071 ] In example 15 the subject matter of the Examples 1 -14 can optionally include an additional drain node on the first fin; an additional MTJ; and an additional contact coupling the additional drain node to the additional MTJ.

[0072] In example 16 the subject matter of the Examples 1 -15 can optionally include wherein the first drain node is included in a first access transistor for accessing the first MTJ and the second drain node is included in a second access transistor for accessing the second MTJ. [0073] In example 17 the subject matter of the Examples 1 -16 can optionally include a spin transfer torque magnetic random access memory (STT-MRAM) that includes the first and second fins.

[0074] Example 18 includes an apparatus comprising: a first semiconductor fin parallel to a second semiconductor fin; a first interconnect line oblique to the first and second fins, the first interconnect line being one of a source line, a bit line, and a word line; a first contact coupling a first transistor node of the first fin to a first memory cell and a second contact coupling a second transistor node of the second fin to a second memory cell; wherein (a) a first vertical axis intersects the first fin and the first interconnect line and a second vertical axis intersects the second fin and the first interconnect line; and (b) the first contact includes sidewalls parallel to the first fin and additional sidewalls orthogonal to the first interconnect line and the second contact includes sidewalls parallel to the second fin and additional sidewalls orthogonal to the first interconnect line.

[0075] In example 19 the subject matter of the Example 18 can optionally include a first via coupling the first memory cell to the first contact and a second via coupling the second memory cell to the second contact; wherein the first via includes a sidewall parallel to a sidewall of the first interconnect line and the second via includes a sidewall parallel to another sidewall of the first interconnect line.

[0076] In example 20 the subject matter of the Examples 18-19 can optionally include wherein the first via is self-aligned to the first interconnect line and the second via is self-aligned to the first interconnect line.

[0077] In example 21 the subject matter of the Examples 18-20 can optionally include wherein the first vertical axis intersects the first via and the second vertical axis intersects the second via.

[0078] Example 22 includes a method comprising: forming first and second semiconductor fins; forming first and second contacts on the first and second fins; forming a first source line oblique to the first and second fins and coupled to the first and second contacts; self aligning first and second vias to the first source line; and coupling the first contact to a first magnetic tunnel junction (MTJ) and the second contact to a second MTJ indirectly through the first and second vias; wherein (a) a first vertical axis intersects the first fin and the first source line and a second vertical axis intersects the second fin and the first source line; and (b) the first contact includes sidewalls parallel to the first fin and additional sidewalls orthogonal to the first source line and the second contact includes sidewalls parallel to the second fin and additional sidewalls orthogonal to the first source line.

[0079] In example 23 the subject matter of the Example 22 can optionally include wherein the first via includes a sidewall parallel to a sidewall of the first source line and the second via includes a sidewall parallel to another sidewall of the first source line.

[0080] In example 24 the subject matter of the Examples 22-23 can optionally include wherein the first vertical axis intersects the first via and the second vertical axis intersects the second via.

[0081 ] The foregoing description of the embodiments of the invention has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed. This description and the claims following include terms, such as left, right, top, bottom, over, under, upper, lower, first, second, etc. that are used for descriptive purposes only and are not to be construed as limiting. For example, terms designating relative vertical position refer to a situation where a device side (or active surface) of a substrate or integrated circuit is the "top" surface of that substrate; the substrate may actually be in any orientation so that a "top" side of a substrate may be lower than the "bottom" side in a standard terrestrial frame of reference and still fall within the meaning of the term "top." The term "on" as used herein (including in the claims) does not indicate that a first layer "on" a second layer is directly on and in immediate contact with the second layer unless such is specifically stated; there may be a third layer or other structure between the first layer and the second layer on the first layer. The embodiments of a device or article described herein can be manufactured, used, or shipped in a number of positions and orientations. Persons skilled in the relevant art can appreciate that many modifications and variations are possible in light of the above teaching. Persons skilled in the art will recognize various equivalent combinations and substitutions for various components shown in the Figures. It is therefore intended that the scope of the invention be limited not by this detailed description, but rather by the claims appended hereto.