[0001] This application claims priority to U.S. Provisional Patent Application No. 62/574,301 , filed on October 19, 2017, entitled "BORON-CONTAINED-NITRIDE- BASED INTERLAYER IN AIGaN/GaN HETEROSTRUCTURE FOR POWER

ELECTRONICS," and U.S. Provisional Patent Application No. 62/716,012, filed on August 8, 2018, entitled "HIGH ELECTRON MOBILITY TRANSISTOR HAVING A BORON NITRIDE ALLOY INTERLAYER AND METHOD OF PRODUCTION," the disclosures of which are incorporated herein by reference in their entirety.

BACKGROUND

TECHNICAL FIELD

[0002] Embodiments of the disclosed subject matter generally relate to a high electron mobility transistor having a boron nitride alloy interlayer interposed between the barrier and buffer layers, and method of production.

DISCUSSION OF THE BACKGROUND

[0003] Gallium nitride- (GaN-) based semiconductors are typically used for high-power electronics due to their large bandgap (3.4 eV of GaN to 6.2 eV of aluminum nitride (AIN)) and high breakdown field (~ 3χ 10 ⁶ V/cm). Additionally, due to its strong polarization fields (spontaneous and piezoelectric polarization), GaN- based heterojunctions are capable of producing high sheet charge densities in excess of 1 ^χ 10 ¹³ cm ^-2 at the heterojunction's interface. Accordingly, high electron mobility transistors (HEMTs) having heterojunction of an aluminum gallium nitride (AIGaN) barrier layer formed on a GaN buffer layer, with an optional thin layer of aluminum nitride between the layers, are conventionally employed. Many efforts have been made to optimize such structures to achieve better device performance. In particular, a large two-dimensional electron gas (2DEG) concentration with high electron mobility would be expected for such device application.

[0004] In the conventional high electron mobility transistors comprising an aluminum gallium nitride/gallium nitride heterojunction, increasing the Al mole fraction in the aluminum gallium nitride barrier layer increases the two-dimensional electron gas concentration, but the alloy scattering effect reduces the electron mobility. Additionally, the higher Al-content in aluminum gallium nitride layer, the larger lattice mismatch between the aluminum gallium nitride layer and the gallium nitride layer, which degrades the interface quality in the heterojunction.

[0005] Thus, it would be desirable to provide for a high electron mobility transistor that has increased two-dimensional electron gas concentration while minimizing the electron mobility reduction caused by the alloy scattering effect and does not suffer from a large lattice mismatch between the buffer and barrier layers.

SUMMARY

[0006] According to an embodiment, a semiconductor device is provided. The semiconductor device includes a Ill-nitride buffer layer, a Ill-nitride barrier layer, and a boron nitride alloy interlayer interposed between the Ill-nitride buffer layer and the Ill-nitride barrier layer. A portion of the Ill-nitride buffer layer includes a two- dimensional electron gas (2DEG) channel that is on a side of the Ill-nitride buffer layer adjacent to the boron nitride alloy interlayer.

[0007] According to an embodiment, a method for forming a semiconductor device is provided. A Ill-nitride buffer layer is formed. A first interlayer is formed on the Ill-nitride buffer layer. A second interlayer is formed on the Ill-nitride interlayer. The first interlayer is one of a Ill-nitride interlayer and a boron nitride alloy interlayer and the second interlayer is the other one of the Ill-nitride interlayer and the boron nitride alloy interlayer. A Ill-nitride barrier layer is formed on the second interlayer. A portion of the Ill-nitride buffer layer includes a two-dimensional electron gas (2DEG) channel that is adjacent to the first interlayer.

[0008] According to an embodiment, a semiconductor device is provided. The semiconductor device includes a Ill-nitride buffer layer, a first interlayer arranged on the Ill-nitride buffer layer, a second interlayer arranged on the Ill-nitride interlayer, and a Ill-nitride barrier layer arranged on the boron nitride alloy interlayer. The first interlayer is one of a Ill-nitride interlayer and a boron nitride alloy interlayer and the second interlayer is the other one of the Ill-nitride interlayer and the boron nitride alloy interlayer. A portion of the Ill-nitride buffer layer includes a two-dimensional electron gas (2DEG) channel that is on a side of the Ill-nitride buffer layer adjacent to the Ill-nitride interlayer.

BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate one or more embodiments and, together with the description, explain these embodiments. In the drawings:

[0010] Figure 1 is a block diagram of a semiconductor device according to embodiments;

[0011] Figure 2 is a flowchart of a method of forming a semiconductor device according to embodiments;

[0012] Figure 3 is a block diagram of a semiconductor device according to embodiments;

[0013] Figure 4 is a flowchart of a method of forming a semiconductor device according to embodiments;

[0014] Figures 5A and 5B are graph of the two-dimensional electron gas (2DEG) concentration and band structure of high electron mobility transistors according to embodiments;

[0015] Figure 6 is a graph of the two-dimensional electron gas peak concentration as a function of the barrier layer thickness according to embodiments; and

[0016] Figure 7 is a graph of the band structure of high electron mobility transistors according to embodiments. DETAILED DESCRIPTION

[0017] The following description of the exemplary embodiments refers to the accompanying drawings. The same reference numbers in different drawings identify the same or similar elements. The following detailed description does not limit the invention. Instead, the scope of the invention is defined by the appended claims. The following embodiments are discussed, for simplicity, with regard to the terminology and structure of high electron mobility transistors.

[0018] Reference throughout the specification to "one embodiment" or "an embodiment" means that a particular feature, structure or characteristic described in connection with an embodiment is included in at least one embodiment of the subject matter disclosed. Thus, the appearance of the phrases "in one embodiment" or "in an embodiment" in various places throughout the specification is not necessarily referring to the same embodiment. Further, the particular features, structures or characteristics may be combined in any suitable manner in one or more embodiments.

[0019] Figure 1 is a block diagram of a semiconductor device according to embodiments. The semiconductor device 100 includes a Ill-nitride buffer layer 105, a Ill-nitride barrier layer 1 15, and a boron nitride alloy interlayer 1 10 interposed between the Ill-nitride buffer layer 105 and the Ill-nitride barrier layer 1 15. A portion of the Ill- nitride buffer layer 105 includes a two-dimensional electron gas (2DEG) channel 107 that is on a side of the Ill-nitride buffer layer 105 adjacent to the boron nitride alloy interlayer 1 10. In the illustrated embodiment, the 2DEG channel 107 is adjacent to the boron nitride alloy interlayer 1 10 without any intervening layers. Those skilled in the art will appreciate that in the 2DEG can extend beyond the Ill-nitride buffer layer 105 into the boron nitride alloy interlayer 1 10 and/or the Ill-nitride barrier layer 1 15. The semiconductor device 100 can also include a Ill-nitride cap layer 120 arranged on the Ill-nitride barrier layer 1 15. It should be recognized that a cap layer is not necessary but improves the overall device performance.

[0020] As will be appreciated, the semiconductor device 100 is a high electron mobility transistor. Thus, the conduction band minimum of the Ill-nitride barrier layer 1 15 must be higher than the conduction band minimum of the Ill-nitride buffer layer 105. Further, the conduction band minimum of the boron nitride alloy interlayer 1 10 must be higher than the conduction band minimum of the Il l-nitride buffer layer 105. Moreover, there must be a polarization difference between the Ill-nitride barrier layer 1 15 and the Ill-nitride buffer layer 105 so that a 2DEG channel is formed on the upper portion of the Ill-nitride buffer layer 105 when the Ill-nitride buffer layer 105 and the Ill-nitride barrier layer 1 15 form a heterojunction. Additionally, there must be a polarization difference between the boron nitride alloy interlayer 1 10 and the buffer layer 105 so that a 2DEG channel is formed on the upper portion of the Ill-nitride buffer layer 105 when the boron nitride alloy interlayer 1 10 and the barrier layer 1 15 form a heterojunction. Further, there must be a polarization difference between the boron nitride alloy interlayer 1 10 and the Ill-nitride buffer layer 105 so that a 2DEG channel is formed on the upper portion of the Ill-nitride buffer layer 105 when the boron nitride alloy interlayer 1 10 and the Ill-nitride buffer layer 105 form a heterojunction. [0021] In an embodiment, the buffer layer 105 can be a gallium nitride (GaN) buffer layer, the boron nitride alloy interlayer 1 10 can be a boron aluminum nitride (BAIN) interlayer, the barrier layer 1 15 can be an aluminum gallium nitride (AIGaN) barrier layer, and the cap layer 120 can be a gallium nitride (GaN) cap layer.

Further, the gallium nitride buffer layer 105 can be, for example, 3 μηι thick. The boron nitride alloy interlayer 1 10 can be, for example, a 1 -2 nm thick boron aluminum nitride interlayer, such as a Bo.i ₄ Alo.86N interlayer. In other embodiments, the boron nitride alloy interlayer can have a thickness in the range of 0.1 to 10 nm. The boron percentage need not be 14% and instead can be any value between 0.1 % and 100%. In other embodiments, the boron nitride alloy interlayer 1 10 can comprise one of: boron, gallium, and nitrogen; boron, indium, and nitrogen; boron, aluminum, gallium, and nitrogen; boron, indium, gallium, and nitrogen; boron, aluminum, indium, and nitrogen; and boron, aluminum, gallium, indium, and nitrogen.

[0022] The aluminum gallium nitride barrier layer 1 15 can, for example, be between 15 and 60 nm thick, and can comprise, for example, Alo.3Gao.7N or graded- composition material. The cap layer 120 can, for example, be 2 nm thick gallium nitride layer. As will be appreciated from Figure 1 , each layer is directly adjacent to, and in physical with, another layer without any intervening layers.

[0023] It will be recognized that the Ill-nitride buffer layer 105, boron nitride alloy interlayer 1 10, I ll-nitride barrier layer 1 15, and Ill-nitride cap layer 120 can comprise other Ill-nitride alloys than those discussed above. For example, the Ill- nitride buffer layer 105 can comprise gallium nitride (GaN), the boron nitride alloy interlayer 1 10 can comprise B0.14AI0.86N, and the Ill-nitride barrier layer 1 15 can comprise Alo.30Gao.70N. In another example, the Ill-nitride buffer layer 105 can comprise gallium nitride (GaN), the boron nitride alloy interlayer 1 10 can comprise B0.13AI0.87N, and the Ill-nitride barrier layer 1 15 can comprise aluminum nitride (AIN). In a further example, the Ill-nitride buffer layer 105 can comprise lno.15Gao.85N, the boron nitride alloy interlayer 1 10 can comprise B0.15AI0.85N, and the I ll-nitride barrier layer 1 15 can comprise gallium nitride (GaN). These are merely examples and should not be considered limiting.

[0024] Figure 2 is a flowchart of a method of forming the semiconductor device 100 of Figure 1 according to embodiments. Initially, a Ill-nitride buffer layer 105 is formed on a substrate (not illustrated) (step 205). A boron nitride alloy interlayer 1 10 is then formed on the Ill-nitride buffer layer 105 (step 210). A Ill-nitride barrier layer 1 15 is formed on the boron nitride alloy interlayer 1 10 (step 215).

Finally, a Ill-nitride cap layer 120 is formed on the Ill-nitride barrier layer 1 15 (step 220). A portion of the Ill-nitride buffer layer 105 includes a two-dimensional gas (2DEG) channel 107 on a side of the Ill-nitride buffer layer 105 that is adjacent to the boron nitride alloy interlayer 1 10.

[0025] The method of Figure 2 can be performed using any suitable technique, such as, for example, metalorganic chemical vapor deposition (MOCVD) and molecular beam epitaxy (MBE). Details on growth conditions that can be used to produce high crystallinity of the boron aluminum nitride interlayer and the heterojunction can be found in X. Li et al., "100-nm thick single-phase wurtzite BAIN films with boron contents over 10%," Phys. Status Solidi B 254 (8), 1600699 (2017), and H. Sun et al., "Band alignment of B0.14AI0.86N / AI0.7Ga0.3N heterojunction," Appl. Phys. Lett. 1 1 1 (12), 122106 (2017).

[0026] Figure 3 is a block diagram of a semiconductor device according to embodiments. Unlike the semiconductor device 100, the semiconductor device 300 includes at least two interlayers. Specifically, a Ill-nitride interlayer 310 is arranged on a Ill-nitride buffer layer 305 and a boron nitride alloy interlayer 315 is arranged on the Ill-nitride interlayer 310. A Ill-nitride barrier layer 320 is arranged on the boron nitride alloy interlayer 315. A portion of the Ill-nitride buffer layer 305 includes a 2DEG channel 307 that is adjacent to the Ill-nitride interlayer 310. Those skilled in the art will appreciate that in the 2DEG channel can extend beyond the Ill-nitride buffer layer 305 into the Ill-nitride interlayer 310, the boron nitride alloy interlayer 315, and/or the Ill-nitride barrier layer 320. The semiconductor device 300 can also include a Ill-nitride cap layer 325 arranged on the nitride barrier layer 320.

[0027] Although Figure 3 illustrates the Ill-nitride interlayer 310 being directly adjacent to the Ill-nitride buffer layer 305 and the boron nitride alloy interlayer 315 being directly adjacent to the Ill-nitride barrier layer 320, the order of these interlayers in the device can be reversed so that the boron nitride alloy interlayer 315 is directly adjacent to the Ill-nitride buffer layer 305 and the Ill-nitride interlayer 310 is directly adjacent to the Ill-nitride barrier layer 320. The arrangement of the Ill-nitride interlayer 310 and the boron nitride alloy interlayer 315 relative to the Ill-nitride buffer layer 305 and the Ill-nitride barrier layer 320 will be depend upon the compositions of the Ill-nitride buffer layer 305 and the Il l-nitride barrier layer 320 and the intended application of the device. [0028] As will be appreciated, the semiconductor device 300 is a high electron mobility transistor. Thus, the conduction band minimum of the Ill-nitride barrier layer 320 must be higher than the conduction band minimum of the Ill-nitride buffer layer 305. Further, the conduction band minimum of both the Ill-nitride interlayer 310 and the boron nitride alloy interlayer 315 must be higher than the conduction band minimum of the Ill-nitride buffer layer 305. Moreover, there must be a polarization difference between the Ill-nitride barrier layer 320 (or the boron nitride alloy interlayer 315 if the boron nitride interlayer is directly adjacent to the Ill-nitride buffer layer 305) and the Ill-nitride buffer layer 305 so that a 2DEG channel is formed on the upper portion of the Ill-nitride buffer layer 305 when the Ill-nitride buffer layer 305 (or the boron nitride alloy interlayer 315) and the Ill-nitride barrier layer 320 form a heterojunction.

[0029] In an embodiment, the Ill-nitride buffer layer 305 can be a gallium nitride (GaN) buffer layer, the Ill-nitride interlayer 310 can be an aluminum nitride interlayer, the boron nitride alloy interlayer 315 can be a boron aluminum nitride interlayer, the Ill-nitride barrier layer 320 can be an aluminum gallium nitride (AIGaN) barrier layer, and the cap layer 325 can be a gallium nitride (GaN) cap layer.

Further, the gallium nitride buffer layer 305 can be, for example, 3 μηι thick. The aluminum nitride interlayer 310 can be, for example, be a 0.5-1 nm thick. In other embodiments, the Ill-nitride interlayer 310 can be a boron nitride alloy interlayer.

[0030] The boron nitride alloy interlayer 315 can be, for example, a 0.5-1 nm thick boron aluminum nitride interlayer, such as a B0.14AI0.86N interlayer. It should be recognized that the Ill-nitride interlayer 310 and the boron nitride alloy interlayer 315 can each have a thickness varying between 0.1 to 10 nm. Further, other

embodiments, the boron nitride alloy interlayer 315 can comprise one of: boron, gallium, and nitrogen; boron, indium, and nitrogen; boron, aluminum, gallium, and nitrogen; boron, indium, gallium, and nitrogen; boron, aluminum, indium, and nitrogen; and boron, aluminum, gallium, indium, and nitrogen.

[0031] The aluminum gallium nitride barrier layer 320 can, for example, be between 5 and 60 nm thick, and can comprise, for example, Alo.3Gao.7N. The gallium nitride cap layer 325 can, for example, be 2 nm thick. As will be appreciated from Figure 3, each layer is directly adjacent to, and in physical with, another layer without any intervening layers.

[0032] It will be recognized that the Ill-nitride buffer layer 305, Ill-nitride barrier layer 320, and Ill-nitride cap layer 325 can comprise other types of Ill-nitrides other than those discussed above. Examples of other layer compositions for the semiconductor device 300 can be similar to those discussed above with regard to the semiconductor device 100.

[0033] Figure 4 is a flowchart of a method of forming the semiconductor device 300 of Figure 3 according to embodiments. Initially, a Ill-nitride buffer layer 305 is formed on a substrate (not illustrated) (step 405). A first interlayer 310 or 315 is formed on the Ill-nitride buffer layer 305 (step 410) and a second interlayer 310 or 315 is then formed on the I ll-nitride interlayer 310 (step 415). The first interlayer is one of a Ill-nitride interlayer and a boron nitride alloy interlayer and the second interlayer is the one of the Ill-nitride interlayer and the boron nitride alloy interlayer. A I ll-nitride barrier layer 320 is formed on the second interlayer 310 or 315 (step 420). Finally, a Ill-nitride cap layer 325 is formed on the Ill-nitride barrier layer 320 (step 425). A portion of the Ill-nitride buffer layer 305 includes a 2DEG channel 307 that is adjacent to the first Ill-nitride interlayer 310 or 315. The method of Figure 4 can be performed using any suitable technique, such as, for example, metalorganic chemical vapor deposition (MOCVD) and molecular beam epitaxy (MBE).

[0034] In order to appreciate the effectiveness of the disclosed interlayers, simulations were performed comparing a number of different interlayers. In the simulation setup, the semiconductor includes a gallium nitride buffer layer, an aluminum gallium nitride barrier layer, and a gallium nitride cap layer. Further, the thickness of the Alo.3Gao.7N barrier layer was initially fixed at 25 nm. The work function used for the Schottky gate is WF = 5.1 eV, resulting in a barrier height of βΦ& = 0.84 eV.

[0035] The calculated two-dimensional electron gas concentration in the aluminum gallium nitride barrier layer based on this device configuration under different interlayer structures is depicted in the table below. In the table below, all interlayers having boron included 14% boron content; however, the boron content can be varied between 0.1 % to 100%. GaN is used as the buffer layer.

[0036]

Interlayer Structure Percentage of 2DEG in 2DEG Density (10 ¹³ /cm ² )

Ternary Layer (%)

0.5 nm BAIN/0.5 nm AIN 0.00 1 .449 with AIN adjacent to the

buffer layer

2 nm Without Interlayer 10.29 1 ,174

2 nm AIN 0.00 1 .539

2 nm BAIN 4.81 2.513

1 nm BAIN/1 nm AIN with 0.00 1 .865

AIN adjacent to the buffer

layer

[0037] It should be recognized that the two cases in the table above for "1 nm Without Interlayer" and "2 nm Without Interlayer" refer to devices without an interlayer and only including an aluminum gallium nitride barrier layer and gallium nitride buffer layer.

[0038] As will be appreciated from the table above, interlayers with 1 nm AIN, 0.5 nm BAIN/0.5 nm AIN, 2 nm AIN, 1 nm BAIN/1 nm AIN have the lowest (zero percentage) two-dimensional electron gas leakage to the AIGaN barrier layer and the 1 nm BAIN/1 nm AIN has the highest two-dimensional electron gas density.

[0039] Figures 5A and 5B illustrate the two-dimensional electron gas concentration in the Alo.3Gao.7N barrier layer and band structure of device structures listed in the table above. As illustrated, an increase of two-dimensional electron gas concentration can be achieved by using 1 nm B0.14AI0.86N as the interlayer instead of 1 nm AIN. Further, an increase of two-dimensional electron gas concentration can be achieved by replacing an interlayer of 2 nm AIN with an interlayer of 2 nm

B0.14AI0.86N. Moreover, based on the band structure, the boron aluminum nitride interlayer increases the barrier height for the electrons to penetrate into Alo.3Gao.7N barrier layer, and thus improves the confinement of two-dimensional electron gas in the channel layer formed in the gallium nitride buffer layer. The boron aluminum nitride alloy of the interlayer will have lattice disorder, which will lead to the alloy scattering and reduce the mobility of high electron mobility transistor. This can be addressed by employing an interlayer heterojunction of, for example, B0.14AI0.86N/AIN as the interlayer to reduce the alloy scattering while maintaining high two- dimensional electron gas concentration.

[0040] The thickness of the Alo.3Gao.7N barrier layer should be optimized to achieve an optimal two-dimensional electron gas concentration. Accordingly, the thickness of the Alo.3Gao.7N barrier layer was varied from 15 to 60 nm while using 2 nm B0.14AI0.86N and 1 nm B0.14AI0.86N/I nm AIN as the interlayer, the results of which are illustrated in Figure 6. As illustrated, a semiconductor device with a 2 nm B0.14AI0.86N interlayer always performs better in terms of the two-dimensional electron gas density than a semiconductor device with 1 nm B0.14AI0.86N/I nm AIN interlayers. Further, the highest two-dimensional electron gas is obtained when the Alo.3Gao.7N barrier thickness is 35 nm, which is the same for both cases regardless of whether a single 2 nm boron aluminum nitride interlayer is used or 1 nm BAIN/1 nm AIN interlayers are used. It should be recognized that if the aluminum content of aluminum gallium nitride barrier layer is increased, the optimal thickness of the barrier layer increases, and vice-versa.

[0041] Figure 7 illustrates the band structures using a 2 nm B0.14AI0.86N interlayer and a 1 nm B0.14AI0.86N/I nm AIN interlayer. In both cases, the AIGaN barrier layer has a fixed barrier thickness of 35 nm. As illustrated in Figure 7, there is a strong band bending at the interface of the AIGaN barrier layer and the interlayer, which creates high two-dimensional electron gas concentration in an upper portion of the gallium nitride buffer layer. Because the alloy scattering effect, which may hurt the mobility in high electron mobility transistors, a semiconductor device having a 35 nm Alo.3Gao.7N barrier layer and 1 nm B0.14AI0.86N/ 1 nm AIN as the interlayer is optimal for high power electronics.

[0042] It should be appreciated that in the discussion above, the boron nitride alloy interlayer includes at least 0.1 % boron, which indicates an intentional inclusion of boron and not that the boron is part of the contact layer as an impurity or contaminant arising during the formation of the device. Similarly, all references above to a layer including aluminum, gallium, or indium should be understood as the layer including 0.1 % aluminum, gallium, or indium, which indicates an intentional inclusion of aluminum, gallium, or indium and not that the aluminum, gallium, or indium is part of the layer as an impurity or contaminant arising during the formation of the device.

[0043] Although exemplary embodiments have been described in connection with high electron mobility transistors, the disclosed interlayers can be used in other types of transistors. [0044] The disclosed embodiments provide a high electron mobility transistor and method of production. It should be understood that this description is not intended to limit the invention. On the contrary, the exemplary embodiments are intended to cover alternatives, modifications and equivalents, which are included in the spirit and scope of the invention as defined by the appended claims. Further, in the detailed description of the exemplary embodiments, numerous specific details are set forth in order to provide a comprehensive understanding of the claimed invention. However, one skilled in the art would understand that various

embodiments may be practiced without such specific details.

[0045] Although the features and elements of the present exemplary embodiments are described in the embodiments in particular combinations, each feature or element can be used alone without the other features and elements of the embodiments or in various combinations with or without other features and elements disclosed herein.

[0046] This written description uses examples of the subject matter disclosed to enable any person skilled in the art to practice the same, including making and using any devices or systems and performing any incorporated methods. The patentable scope of the subject matter is defined by the claims, and may include other examples that occur to those skilled in the art. Such other examples are intended to be within the scope of the claims.