[Title of Invention]

HIGH ELECTRON MOBILITY TRANSISTOR

[Technical Field]

[0001]

The present invention relates generally to semiconductor device such as high electron mobility transistors for high frequency applications.

[Background Art]

[0002]

Semiconductor devices have a significant role in solving energy challenges. Specifically, nitride power transistors have great potential in the application of advanced transportation systems, reliable energy delivery networks and many new approaches for high-efficiency electricity generation and conversion. Those systems rely on converters to step-up or step-down electric voltages. Currently, most of these devices are made of silicon (Si). However, the limited breakdown voltage and frequency response of Si, and its higher resistance make the currently available commercial devices bulky, heavy and inappropriate for future power applications. As an alternative, gallium nitride (GaN) devices have achieved record combination of high- voltages, high frequency response and low on-resistances for power applications.

[0003]

GaN power devices, such as the GaN-based high electron mobility

transistors (HEMTs), are regarded as one of the most promising candidates for high-power, high-voltage and high frequency applications. GaN HEMTs have achieved up to 10 times higher power density of GaAs HEMTs with much larger breakdown voltage (VB) and current density, as well as a high cut-off frequency of over 400 GHz. State-of-the-art power levels have been demonstrated on silicon carbon (SiC) substrates with total output powers of 800 W at 2.9 GHz and over 500 W at 3.5 GHz. However, for the high-power applications, such as high-power motors, a higher output power, i.e. 3-5 kW, is desired, which requires a further enhancement of output power of semiconductor devices.

[Summary of Invention]

[0004]

Some embodiments are based on a recognition that a number of different methods can be used to enhance the output power of semiconductor devices using different principles. For example, it is possible to increase the breakdown voltage of a semiconductor device by depleting a carrier channel in the semiconductor device by a vertical electric field. Other methods for enhancing device power capability include thermal management and reduction of the power loss due to parasitic leakage of the carrier charge.

[0005]

Each method can enhance power capability of the semiconductor device only to some extent. However, some embodiments are based on recognition that in some circumstances the combination of those methods can provide a synergy effect on the power output of the semiconductor device.

[0006]

For example, some embodiments are based on recognition that the thermal management of the semiconductor device can be performed by a thermal spreading layer of material having thermal conductivity larger than the thermal conductivity of a material in the semiconductor structure forming the carrier channel. Similarly, the leakage of the carrier charge can be reduced by a layer of material having a bandgap larger than the bandgap of a material in the semiconductor structure forming the carrier channel. Some embodiments are based on realization that it is possible to provide such a layer of material that can perform both of those functions. [0007]

For example, some embodiments are based on recognition that Graphene has the capability of achieving lower thermal resistance. In addition, the bandgap of the Graphene can be made larger than the bandgap of a material in the

semiconductor structure forming the carrier channel.

[0008]

Some embodiments are based on another recognition the thermal resistance of the 2-DEG channel is inversely proportional to the distance between the 2-DEG channel and the heat sink and directly proportional to the thermal conductivity of the layer performing the thermal spreading. Some embodiments are based on recognition that the graphene can be made atomically thin. The atomically thin graphene layer can be placed closer to the 2-DEG channel, while the thermal conductivity of the atomically thin graphene layer is sufficient to dissipate the heat to the heat think thermally connected to the graphene layer.

[0009]

In such a manner, because the graphene has a high thermal conductivity and placed in the proximity to the channel layer, the overall thermal resistance of the HEMT of some embodiments is reduced. This reduction is beneficial. For example, for RF power transistor having a heat sink, the reduction of the thermal resistance between the 2-DEG channel of the transistor and the heat sink increases the possible power density that the transistor can dissipate before undesirable high temperature effects, such as reduced electron mobility.

[0010]

Accordingly, one embodiment discloses a high electron mobility transistor (HEMT), including a semiconductor structure including a cap layer and a channel layer forming a heterojunction, such that a two dimensional electron gas (2-DEG) channel is formed at the interface of cap layer and the channel layer; a source electrode and a drain electrode arranged on the cap layer to make electrical contacts with the 2-DEG channel; a gain electrode arranged on the cap layer between the source electrode and the drain electrode along the length of the HEMT to modulate the conductivity of the 2-DEG channel; a substrate; and an atomically thin graphene layer arranged between the substrate and the semiconductor structure. [Brief Description of Drawings]

[0011]

[Fig- 1]

Figure 1 shows a 2-D cross section of a high electron mobility transistor (HEMT) with graphene back barrier layer according to some embodiments.

[Fig. 2]

Figure 2 shows a top view of the device of Figure 1

[Fig. 3]

Figure 3 shows a plot of power dissipation with respect to peak temperature in the channel formed by the device of Figure 1.

[Fig. 4]

Figure 4 shows a cross section of HEMT with Graphene back barrier and top graphene thermal spreading layer according to some embodiments.

[Description of Embodiments]

[0012]

Figure 1 shows the 2-D cross section view of the semiconductor device, such as high electron mobility transistor (HEMT), according to some embodiments. The device has a semiconductor structure including a cap layer 101 and a channel layer 102 forming a heterojunction, such that a two dimensional electron gas (2- DEG) channel 107 is formed at the interface of cap layer and the channel layer.

The device also includes a substrate 106 and an atomically thin graphene layer 104 arranged between the substrate and the semiconductor structure. [0013]

In some implementations the material of the channel semiconductor structure includes one or combination of gallium nitride (GaN), indium gallium nitride (InGaN), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), aluminum nitride (AIN), aluminum gallium arsenide (AlGaAs), aluminum arsenide (AlAs), and indium aluminum gallium arsenide (InAlGaAs). Additionally, or alternatively, the source and the drain semiconductor region includes one or combination of gallium nitride (GaN), indium gallium nitride (InGaN), gallium arsenide (GaAs), indium gallium arsenide (InGaAs).

[0014]

In some embodiments, the device can also include additional layers. For example, the device can also include a back barrier layer 103 and a buffer layer 105. The device can also include a thermal energy spreading layer including the atomically thin graphene layer 104. The thermal energy spreading layer includes an atomically thin‘Graphene’ layer configured to be connected thermally to a heat sink. For example, the heat sink can be a metal slab attached to the substrate.

Typically, the heat sink is not a part of electronic device but a part of the

packaging of the device.

[0015]

The device also includes a source electrode 110 and a drain electrodel30 arranged to make electrical contact with the 2-DEG channel 107. A gate electrode 120 on top of the cap layer is provided to modulate the conductivity of channel. In some implementations, the back barrier layer 103 is a nitride semiconductor which has higher bandgap than the channel layer and the purpose of this layer is to provide carrier confinement and reduce the direct leakage current from source to drain.

[0016] Some embodiments are based on recognition that in order to improve the power capability of HEMT, it can be beneficial to reduce the thermal resistance between the channel and the heat sink. Otherwise when the HEMT is operated at high power mode, the device temperature increases beyond the critical temperature of 150 degrees Celsius, which in turn degrades the mobility and thus the current.

[0017]

Some embodiments are based on recognition that thermal resistance is inversely proportional to the distance between the channel and the heat sink; and directly proportional to the thermal conductivity of the thermal spreading layer. Since graphene has a very high thermal conductivity, in various embodiments, the graphene layer is placed in proximity, e.g., within tens of nano-meters, to the channel layer to reduce the overall thermal resistance of the HEMT device. A lower thermal resistance is a figure of merit for higher device performance.

[0018]

Figure 2 shows the top view of a device according to one embodiment exhibiting the relative arrangement of source, gate and drain electrodes. In this embodiment, the distance between the source and the gate L _S D is higher than the distance between the Gate and the Drain L _GD . In some implementations, L _S D is as low as possible because high L _S D increases source resistance which in turn decreases the linearity of the device. However, L _S D cannot be made very small as it increases the parasitic capacitances which decreases cut off frequency. For most applications L _SD is in the rage of few micrometers for power electronic

applications and hundreds of nanometers for radio frequency applications. L _GD depends on the break down voltage of the device. Higher break down voltage needs higher L _GD . L _GD also depends on the material property of the semiconductor that would be used to form the channel, a wide band gap material would give higher breakdown voltage at a relatively lower L _GD . For example if the breakdown voltage of the device is V _B R then a GaN based device L _CD =

i um. The break- down voltage of any RF transistor has a direct relation with the maximum RF output power, n _a xOa _/? ^~ V _k n _e e) ² Therefore, a high breakdown voltage gives higher output power.

[0019]

Figure 3 shows a plot of the power dissipation vs peak temperature rise (P _diss vs Tp _eak ) within the device according to some embodiments. The slope of this plot demonstrates the thermal resistance of the device. As shown in this figure, the thermal resistance of the HEMT according to some embodiments is 6x lower than a HEMT device without the atomically thin graphene layer. When voltages are applied at the drain and gate electrodes of the transistor current start to flow through the transistor. Most of the voltage applied at the drain terminal is dropped in the channel region between the gate and drain terminal because of this region being more resistive which in turn makes this region where most of the power is being dissipated. With higher power dissipation the temperature of this region goes up.

[0020]

The device of various embodiments can be contrasted with HEMT, in which the generated heat spreads throughout the epi-layers and goes to the environment through heat sink connected to the back of the substrate. Since, there is no highly thermally conductive layer placed close to the channel, the thermal resistance of the heat transport path is quite high. In contrast to that, in the device of some embodiments has a highly thermally conductive layer of Graphene placed a few nm away from the channel making the thermal resistance of the device much lower which in turn provides high power performance.

[0021]

Figure 4 shows a cross section of HEMT with Graphene back barrier and a top graphene thermal spreading layer according to one embodiment. In his embodiment, the HEMPT includes a top graphene thermal spreading layer 109 arranged on a supportive layer 108 above the electrodes. For example, the layer 108 is a dielectric layer encapsulating the source, the drain, and the gate electrodes, such that the top graphene layer is deposited atop of the dielectric layer. In such a manner, the HEMT of Figure 4 includes multiple graphene layers including a first graphene layer and a second graphene layer, wherein the first graphene layer is arranged below the semiconductor structure and the second graphene layer is arranged above the semiconductor structure. Because of two thermal spreading layers the heat generated in the channel region has more thermally conductive paths to go to the heat sink and be dissipated in the environment. This additional thermal spreading layer lowers the thermal resistance of the device even further.

[0022]

Different embodiments use different techniques for fabricating a

semiconductor device according to some embodiments.

[0023]

In some implementations, the material of the heterostructure is selected, in such a way, that there forms a 2-DEG channel at the interface of each of the heterostructures. According to some embodiments, various methods can be adopted for the growth and formation of these heterostructure semiconductor layers, including but not limited to a Chemical Vapor Deposition (CVD), a Metal- Organic-Chemical-Vapor-Deposition (MOCVD), a Molecular Beam Epitaxy (MBE), a Metal-Organic Vapor Phase Epitaxy (MOVPE) and a Plasma Enhanced Chemical Vapor Deposition (PECVD) and a microwave plasma deposition system.

[0024]

In some implementations, the device is formed using deposition of gate dielectric to electrically isolate the gate metal form the channel region which reduces the gate leakage and improve the RF performance of the transistor. Then the gate metal deposition is done, by using one or combination of Lithography-^ Metal Deposition -> Lift-off and Metal deposition -> Lithography -> Etching. [0025]

Here the lithography could be performed using, including but not limited to photo-lithography, electron-beam lithography. Metal deposition can be done using one or combination of an ebeam deposition, a joule evaporation, a chemical vapor deposition and a sputtering process.