Title:
HIGH FREQUENCY CIRCUIT, AND COMMUNICATION DEVICE
Document Type and Number:
WIPO Patent Application WO/2021/256088
Kind Code:
A1
Abstract:
The present invention limits the output power of an amplification circuit more accurately. This high frequency circuit is provided with an amplification circuit (2), a bias circuit (3), a bias control circuit (54), a comparing unit (6), a signal input terminal, an antenna terminal, an attenuating circuit (4), and a control unit (55). The amplification circuit (2) includes a specific transistor (Tr2A). The bias circuit (3) supplies a bias current or a bias voltage to the input terminal of the specific transistor (Tr2A). The bias control circuit (54) supplies a control current or a control voltage to the bias circuit (3). The comparing unit (6) compares a power source voltage (Vcc) of a power source terminal (11) connected to the output terminal of the specific transistor (Tr2A) with a threshold voltage (Vref). The attenuating circuit (4) is connected to a signal pathway between the signal input terminal and the antenna terminal, and is capable of attenuating high frequency signals. The control unit (55) changes the amount of attenuation of the attenuating circuit (4) in accordance with the comparison result obtained by the comparing unit (6).
Inventors:
HIROBE MASAKAZU
Application Number:
PCT/JP2021/016502
Publication Date:
December 23, 2021
Filing Date:
April 23, 2021
Export Citation:
Assignee:
MURATA MANUFACTURING CO (JP)
International Classes:
H03G3/30; H03F1/30; H03F1/52; H03F3/24
Foreign References:
| JP2005539448A | 2005-12-22 | |||
| JP2012151539A | 2012-08-09 | |||
| JP2012134612A | 2012-07-12 | |||
| JP2006319508A | 2006-11-24 | |||
| JP2008113223A | 2008-05-15 | |||
| JP2020072468A | 2020-05-07 | |||
| JP2019110505A | 2019-07-04 | |||
| US20200169235A1 | 2020-05-28 |
Attorney, Agent or Firm:
HOKUTO PATENT ATTORNEYS OFFICE (JP)
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