FIELD OF THE INVENTION

The present invention relates to the field of Frequency Control Products. More specifically, it provides a high frequency reference device characterized by small size, low power consumption, high performance, low complexity, and low cost.

BACKGROUND OF THE INVENTION

Currently, Crystal Oscillators (XO), Temperature Compensated Crystal Oscillators (TCXO), Voltage Controlled Crystal Oscillators (VCXO), Voltage Controlled Temperature Compensated Crystal Oscillators (VCTCXO), and Oven Controlled Crystal Oscillators (OCXO) that are characterized by small size (i.e., having a footprint of about 14mm x 9mm or smaller), low power consumption, high performance, and low cost are readily available for frequencies up to about 52MHz. Several performance issues associated with crystal resonators and oscillator circuits have prevented such oscillators from becoming available for frequencies beyond that. The said performance issues include higher aging rates, more frequent activity dips, and high power consumption.

Presently available high frequency crystal oscillators are characterized by high complexity and consequently, by increased size, high power consumption, and high cost. The complexity of the topologies implemented in presently available high frequency oscillators does not lend itself to miniaturization, lowering power consumption and cost, which leaves the needs of the industry unaddressed.

The high frequency reference device of the present invention offers a useful alternative to the presently available high frequency crystal oscillators by providing a high frequency reference device that is characterized by small size, high performance, low power consumption, structural simplicity, and low cost. The device of the present invention comprises an integrated low frequency crystal oscillator (XO, or TCXO, or VCXO, or VCTCXO, or OCXO), a filter, and a low cost buffer, and allows to extend the output frequency up to about 250M Hz (the exact limit is defined by the gain-bandwidth product characteristic of the output buffer used in the device of this invention). Power consumption in at least some embodiments of the device of the present invention is about 1/3 of that of currently available high frequency oscillators of similar performance. The high frequency reference device of the present invention can be assembled in small size packages (from about 14mm x 9mm and down to 5mm x 3mm or smaller), in both PCB and ceramic implementations.

SUMMARY OF THE INVENTION In broad terms the invention provides a high frequency reference device that is characterized by small size (i.e., having a footprint that is not substantially larger than 14mm x 9mm), low power consumption, low complexity, and low cost.

The invention offers a frequency reference device for generating a signal of a required nominal frequency, comprising (1) an integrated crystal oscillator arranged to generate a signal of frequency that is a fraction of the required nominal frequency, (2) a filter to pass the required nominal frequency, and (3) a buffer for outputting the signal of the required nominal frequency.

In different embodiments of the high frequency reference device of the present invention the said integrated crystal oscillator can be either a standard integrated Crystal Oscillator (XO), or an integrated Temperature Compensated Crystal Oscillator (TCXO), or an integrated Voltage Controlled Crystal Oscillator (VCXO), or an integrated Voltage Controlled Temperature Compensated Crystal Oscillator (VCTCXO), or an integrated Oven Controlled Crystal Oscillator (OCXO).

In at least some embodiments the said filter is a passive band pass and band reject filter. The band pass and band reject filter may comprise an inductor used in both the band pass and the band reject circuits. The band pass and band reject filter may comprise a capacitive divider to control the output signal level, or for impedance matching, or for both of these purposes. Alternatively, the filter may be implemented as comprising a mutually coupled pair of tuned circuits, with or without a capacitive divider to control the output signal level, for impedance matching, or for both.

In at least some embodiments the said buffer is a logic integrated circuit arranged as an amplifier and buffer for the said frequency reference device's output signal.

DEFINITION AND INTERPRETATIONS

In this specification and claims the following definitions and interpretations of terms apply:

"Small size" as applied to frequency reference devices means having a footprint of not substantially larger than 14mm x 9mm. "Integrated" as applied to crystal oscillators means a crystal oscillator comprising a semiconductor integrated circuit wherein at least the oscillator's electronic circuit is incorporated in the said integrated circuit.

"Low frequency" as applied to crystal oscillators or frequency reference devices means any frequency that is not substantially higher than 52MHz.

"High frequency" as applied to crystal oscillators or frequency reference devices means any frequency that is substantially higher than 52MHz.

"Fraction" means a number equal to 1/N, where N can be any positive integer number greater than 1. Examples of such fractions are: 1/2, 1/3, 1/4, 1/5, 1/6, 1/7, etc. "Even order fraction" means a fraction equal to l/2n, where n can be any positive integer number. Examples of even order fractions are: 1/2, 1/4, 1/6, etc.

"Odd order fraction" means a fraction equal to l/(2n+l), where n can be any positive integer number. Examples of odd order fractions are: 1/3, 1/5, 1/7, etc.

"Comprising" means "consisting at least in part of"; and means that features other than that or those prefaced by the term may also be present; "comprise" and "comprises" have a similar meaning.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention is further described with reference to the accompanying figures in which:

FIG. 1 shows the main functional blocks of a possible embodiment of a frequency reference device of the present invention.

FIG. 2 shows an example circuit of a filter used in the device of the present invention.

FIG. 2A shows the Bode plot for the filter circuit shown in FIG. 2.

FIG. 3 shows another example circuit of a filter used in the device of the present invention.

FIG. 3A shows the Bode plot for the filter circuit shown in FIG. 3. FIG. 4 shows a typical phase noise plot of a 98.304MHz temperature compensated device of the present invention.

FIG. 5 shows the waveform of the output signal and some of the waveform parameters. DETAILED DESCRIPTION OF THE INVENTION

The present invention sets out to provide a high frequency reference device that is characterized by small size, high performance, low power consumption, low complexity, and low cost.

The main functional blocks of the frequency reference device of the present invention are shown in FIG. 1 that illustrates one of the possible embodiments. The main functional blocks comprise an integrated low frequency crystal oscillator (which in the embodiment shown is a VCTCXO), a filter, and a buffer.

Advantageously, the low frequency crystal oscillator can be a commercial off-the-shelf integrated XO, TCXO, VCXO, VCTCXO, or OCXO type. Importantly, it generates an output signal having a waveform that contains significant levels of harmonics; such waveform may be a square wave (e.g., CMOS output), a clipped sinewave, or other known suitable waveform type. The frequency of the signal generated by the said integrated low frequency oscillator is an even order fraction or an odd order fraction of the required output frequency of the frequency reference device. For applications where high frequency versus ambient temperature stability is required, low frequency integrated TCXOs or VCTCXOs with nominal frequency of up to 52MHz and frequency vs temperature stability between ±100ppb and ±2.5ppm are readily available as standard products from various commercial sources. For even higher stability, an integrated OCXO can be deployed as the base oscillator in the device of this invention.

The integrated crystal oscillator utilized in the high frequency reference device of this invention can be either a fundamental mode crystal oscillator, or a crystal oscillator arranged to operate in an overtone mode. An important design consideration of the device of this invention is suppression of unwanted harmonics. For example, when using an integrated low frequency oscillator with a square wave output (i.e., with high level of odd harmonics), two main practical limitations apply to the integrated low frequency crystal oscillators that can be used in the device of the present invention. Firstly, the rise and fall time of the output square wave will eventually diminish the harmonic levels faster than the Fourier analysis of an ideal square wave would indicate. This results in a limitation of about the 9 ^th harmonic as a practically usable output from the low frequency integrated crystal oscillator. Secondly, the duty cycle of the low frequency integrated crystal oscillator's output waveform is not perfect and may deviate by up to ±5% from the ideal 50/50 mark-space ratio. This deviation gives rise to the otherwise suppressed even harmonics and will result in some level of 2 ^nd , 4 ^th , 6 ^th , etc. harmonics. Depending on the magnitude of the duty cycle deviation and the tolerance of the application circuit, the impact of these harmonics can be sufficiently minimized by the Q of the filter. As the selected order of the required harmonic is increased, the required buffer gain will also increase and the phase noise of the output signal will also degrade by a similar amount. For a 3 ^rd harmonic device the gain loss compared to fundamental frequency is 20 x (log3) = 9.54dB. Given that the fundamental frequency output of an integrated CMOS crystal oscillator on a 3.3V supply will approach (with light loading) 3.3V p-p, the 3 ^rd harmonic will still be a sufficiently strong signal of about IV p-p. Phase noise of the resulting triple frequency output signal will be also degraded by about 9.54dB.

The low frequency integrated crystal oscillator (integrated XO, TCXO, VCXO, VCTCXO, or OCXO) sets the high frequency device's performance parameters such as frequency stability versus temperature, sensitivity to supply voltage variations, and voltage control parameters, as the circuitry of the filter and the buffer has little or no impact on the performance of the base integrated crystal oscillator.

The main function of the filter is to pass the required harmonic frequency but largely reject all other harmonics, including those that are lower than the required output frequency. The filter can be a band pass filter or a band pass and band reject filter as will be described further below. The filter should present minimal signal loss and preferably offer some Q to the wanted harmonic signal. Given that the base integrated crystal oscillator (integrated XO, TCXO, VCXO, VCTCXO, or OCXO) has a relatively low output impedance and the buffer following the filter has a high input impedance, there are few constraints on the filter. Power matching is not a necessary concern either.

An example of a simple filter that can be used in the device of this invention is a passive filter comprising a single inductor deployed as part of a series resonant circuit to suppress the fundamental frequency and of a parallel resonant circuit to pass the wanted harmonic to the buffer stage. A circuit of such a filter is shown in FIG. 2. In this circuit, the value of capacitor CI is chosen to be quite small (high impedance) so as not to present the integrated crystal oscillator's output impedance directly to the parallel resonant circuit comprised of inductance LI and the series combination of C2, C3, and C4. The parallel tank circuit comprised of LI, C2, C3, and C4 resonates at the selected harmonic frequency, with C3 and C4 providing, if required, a means of controlling the signal level presented to the buffer, or a means of impedance matching, or both. The series resonant circuit comprised of LI and C2 presents a low impedance to ground at the series resonant frequency and is arranged to reject the fundamental frequency. This filter circuit has limited Q at the wanted harmonic and the adjacent harmonics are not greatly suppressed, which may or may not be a concern depending on whether harmonic levels are important for the application. That said, for a 3 ^rd harmonic 98.304MHz device the harmonics are 32.768MHz away from the carrier and often well outside the bandwidth of any downstream circuitry, so many applications will easily tolerate them providing they are 30dB or more lower than the wanted carrier signal. The Bode plot of the filter circuit in FIG. 2 is shown in FIG. 2A.

FIG. 3 shows another possible implementation example of the filter used in the device of this invention. This filter circuit has no explicit circuitry for the rejection of the fundamental frequency; instead, it relies on the combined Q of the two circuits tuned to the wanted harmonic frequency, and the enhanced skirt selectivity suppresses the unwanted harmonics. In this circuit, CI provides a high impedance feed into the resonant circuit consisting primarily of C2 and LI. A second tuned circuit consists primarily of the series combination C3, C4 and inductance L2. Inductor L3 is common to both tuned circuits and functions as a low impedance coupling element transferring energy from the first tuned circuit to the second one. The two tuned circuits in this configuration represent a mutually coupled pair. Capacitors C3 and C4 allow, if required, to control the input signal level into the buffer stage, or to carry out impedance matching, or both.

Inductor L3 could be replaced with a smaller size capacitor of a similar reactance value at the wanted harmonic frequency. The close-in passband will in this case be very similar, however the rejection of the fundamental and sub-harmonic frequencies will be poorer due to increased coupling at low frequencies.

The Bode plot of the filter circuit in FIG. 3 is shown in FIG. 3A.

Harmonic rejection achieved by using the filter circuit of FIG. 3 in devices of this invention is illustrated by data for five devices of 98.304MHz output frequency shown in the following table:

Harmonic levels (normalized to OdB at 98.304MHz). V _D D=3.3V. Room temperature.

Load=100R+50R instrument.

98.304MHz TCXO samples dBc

Note: 6th harmonic (2nd of 98.304MHz) level is dependent on integrated TCXO and inverter duty cycles.

9th harmonic (3rd of 98.304MHz square wave) is expected to be about lOdB below carrier level. It should be noted that with either type of filter both of the two harmonics closest to the wanted output frequency are even order harmonics and therefore are greatly attenuated by the 1:1 duty cycle of the square wave. Thus, for a 98.304MHz output device using a 32.768MHz integrated CMOS output oscillator as the initial signal source the harmonics at 65.536MHz and 131.072MHz are almost absent in the source even before they are further attenuated by the filter. This means that the 98.304MHz output signal is spurious free at least within these bandwidth limits and both harmonics are heavily suppressed.

The output buffer can be a low cost logic gate (inverter) biased into linear mode of operation. The buffer should have a gain-bandwidth product as suitable for the required output frequency. The buffer provides amplification and output limiting while presenting a moderately high load impedance to the filter, yet a low output impedance drive (a simple inverter logic gate can drive less than 200 ohm load). Excellent results have been obtained, for example, with the buffered LVC CMOS inverter SN74LVC1G04; this logic component has much higher gain than its unbuffered counterpart; it also offers lower input capacitance (although the latter can be readily resonated out with the choice of filter capacitors anyway). Noise of this logic gate device is around 8-10dB lower than that of a typical integrated TCXO, so it will in no way dominate the output signal noise parameters. Gain will vary across temperature range, being highest at low temperature and this will result in very low integrated jitter figures at -40°C and higher jitter at +85°C. Noise floor of the TCXO also increases at higher temperatures. For very high frequencies (higher than 150MHz) the AUC family offers better performance, although it currently limits the supply voltage to not more than 2.7V. An unbuffered logic gate inverter (such as, for example, SN74LVC1GU04) could also be arranged as an amplifier and output buffer in the design of the present invention. Despite its designation as "unbuffered", it can be arranged to serve the function of a buffer by presenting a relatively high input impedance to the filter's output signal and relatively low output impedance to drive the device's load. Devices implemented with an "unbuffered" component (when justified, perhaps, by lower cost) do therefore fall within the scope of the concept and claims of the present invention. Compared to a buffered logic inverter such as, for example, SN74LVC1G04, an "unbuffered" inverter has the disadvantages of lower gain, higher input capacitance, and low output current capability.

FIG. 4 shows the typical phase noise plot of the output signal of a 98.304MHz frequency reference device of the present invention; the device was designed using a 32.768MHz CMOS output integrated TCXO, with the 3 ^rd harmonic (98.304MHz) selected and buffered. Of particular interest to telecommunication applications is the jitter value in the integration band of 12kHz to 20MHz, which in this case is 164fs (femtoseconds). This figure is considerably helped by the abrupt roll-off after about 3MHz offset due to the filter bandwidth. This jitter performance is better than that of most PLL-based approaches and is achieved at a fraction of PLL-based approaches' power consumption budget. The device uses off-the-shelf commercially available components and can be arranged into a single small size package with a PCB or a ceramic substrate.

The table below shows a listing of certain performance parameters gathered from a build of ten 98.304M Hz TCXO devices of the present invention:

Of note is the good DC stability of the buffer across temperature when driving a load of 150Ω (no load IDD is typically 10.8mA at 25°C). Output drive level is also well controlled, with a maximum change of 0.3d B across temperature when driving a 150Ω load.

FIG. 5 shows the waveform of the output signal and some of the waveform parameters when using the LVC family logic buffer on a supply voltage of 3.3V. The waveform exhibits fast rise and fall times, and the duty cycle is well within the acceptable norm of ±5%.