CHEN YI-WEN (US)
XIU XIAOYU (US)
MA TSUNG-CHUAN (US)
CHEN WEI (US)
WANG XIANGLIN (US)
YU BING (CN)
JHU HONG JHENG (CN)
CHEN YI WEN (US)
US20090175349A1 | 2009-07-09 |
BENJAMIN BROSS , JIANLE CHEN , SHAN LIU , YE-KUI WANG: "Versatile Video Coding (Draft 8)", 17. JVET MEETING; 20200107 - 20200117; BRUSSELS; (THE JOINT VIDEO EXPLORATION TEAM OF ISO/IEC JTC1/SC29/WG11 AND ITU-T SG.16 ), no. JVET-Q2001-vE, 12 March 2020 (2020-03-12), pages 1 - 510, XP030285390
H.-J. JHU (KWAI), X. XIU (KWAI), Y.-W. CHEN (KWAI), T.-C. MA (KWAI), X. WANG (KWAI INC.): "AHG9: On SPS inter slice related syntaxes", 130. MPEG MEETING; 20200420 - 20200424; ALPBACH; (MOTION PICTURE EXPERT GROUP OR ISO/IEC JTC1/SC29/WG11), 6 April 2020 (2020-04-06), XP030286551
Z. DENG (BYTEDANCE), LI ZHANG (BYTEDANCE), Y.-K. WANG (BYTEDANCE): "AHG9: PH and SH syntax cleanups", 17. JVET MEETING; 20200107 - 20200117; BRUSSELS; (THE JOINT VIDEO EXPLORATION TEAM OF ISO/IEC JTC1/SC29/WG11 AND ITU-T SG.16 ), 30 December 2019 (2019-12-30), XP030222607
CLAIMS What is claimed is: 1. A method for decoding a video signal, comprising: receiving, by a decoder through a bitstream, arranged syntax elements in sequence parameter set (SPS) level, wherein the arranged syntax elements in the SPS level are arranged so that functions of related syntax elements are grouped in versatile video coding (VVC) syntax at a coding level; receiving, by the decoder through the bitstream and in response to multiple syntax elements satisfy a predefined condition, a second syntax element immediately after the multiple syntax elements; and performing, by the decoder through the bitstream, a related syntax element function to video data from the bitstream in accordance with the multiple syntax elements and the second syntax element. 2. The method of claim 1, wherein the functions of related syntax elements comprise intra tools, inter tools, screen content tools, transform tools, quantization tools, loop filter tools, and partition tools. 3. The method of claim 1, wherein receiving, by the decoder, the arranged syntax elements in the SPS level comprises: receiving, by the decoder, the arranged syntax elements in the SPS level, wherein the arranged syntax elements in the SPS level are arranged by: receiving a sps_mmvd_enabled_flag value; determining that sps_mmvd_enabled_flag flag is equal to 1; receiving a sps_fpel_mmvd_enabled_flag value; determining that sps_mmvd_enabled_flag flag is not equal to 1; and setting a sps_fpel_mmvd_enabled_flag value. 4. The method of claim 1, wherein receiving, by the decoder, the arranged syntax elements in the SPS level comprises: receiving, by the decoder, the arranged syntax elements in the SPS level, wherein the arranged syntax elements in the SPS level are arranged by: receiving a sps_transform_skip_enabled_flag flag; determining that sps_transform_skip_enabled_flag flag is equal to 1; receiving a log2_transform_skip_max_size_minus2 value; receiving a sps_bdpcm_enabled_flag flag; determining that sps_transform_skip_enabled_flag flag is not equal to 1; setting a log2_transform_skip_max_size_minus2 value; setting a sps_bdpcm_enabled_flag value; receiving a sps_weighted_pred_flag flag; receiving a sps_weighted_bipred_flag flag; receiving a long_term_ref_pics_flag flag; determining that sps_video_parameter_set_id value is larger than 1; receiving a sps_inter_layer_ref_pics_present_flag flag; determining that sps_video_parameter_set_id value is not larger than 1; setting a sps_inter_layer_ref_pics_present_flag flag; receiving a sps_idr_rpl_present_flag flag; receiving a rpl1_same_as_rpl0_flag flag; receiving one or more num_ref_pic_lists_in_sps value; and receiving a sps_ref_wraparound_enabled_flag flag. 5. The method of claim 1, wherein receiving, by the decoder, the arranged syntax elements in the SPS level comprises: receiving, by the decoder, the arranged syntax elements in the SPS level, wherein the arranged syntax elements in the SPS level are arranged by: receiving a sps_mmvd_enabled_flag value; determining that sps_mmvd_enabled_flag flag is equal to 1; receiving a sps_fpel_mmvd_enabled_flag value; receiving a six_minus_max_num_merge_cand value; receiving a sps_sbt_enabled_flag value; receiving a sps_affine_enabled_flag value; determining that sps_affine_enabled_flag flag is equal to 1; receiving a five_minus_max_num_subblock_merge_cand value; receiving a sps_affine_type_flag value; determining that sps_amvr_enabled_flag flag is equal to 1; receiving a sps_affine_amvr_enabled_flag value; receiving a sps_affine_prof_enabled_flag value; determining that sps_affine_prof_enabled_flag flag is equal to 1; receiving a sps_prof_control_present_in_ph_flag value; receiving a sps_bcw_enabled_flag value; receiving a sps_ciip_enabled_flag value; determining that MaxNumMergeCand value is larger than or equal to 2; receiving a sps_gpm_enabled_flag value; determining that sps_gpm_enabled_flag flag is equal to 1 and MaxNumMergeCand value is larger than or equal to 3; receiving a max_num_merge_cand_minus_max_num_gpm_cand value; receiving a log2_parallel_merge_level_minus2 value; 6. The method of claim 1, further comprising: receiving, by the decoder, arranged syntax elements in picture parameter set (PPS) level so that functions of related syntax elements are grouped in VVC syntax at a coding level. 7. The method of claim 6, wherein receiving, by the decoder, arranged syntax elements in the PPS level comprises: receiving, by the decoder, the arranged syntax elements in the PPS level, wherein the arranged syntax elements in the PPS level are arranged by: determining that a pps_cu_chroma_qp_offset_list_enabled_flag flag is set; setting a num_ref_idx_default_active_minus1 value; receiving a pps_weighted_pred_flag flag; receiving a rpl_info_in_ph_flag flag; determining that a pps_ref_wraparound_enabled_flag flag is set; and receiving a deblocking_filter_control_present_flag flag. 8. The method of claim 6, wherein receiving, by the decoder, arranged syntax elements in the PPS level comprises: receiving, by the decoder, the arranged syntax elements in the PPS level, wherein the arranged syntax elements in the PPS level are arranged by: receiving a rpl1_idx_present_flag flag; receiving a pps_weighted_pred_flag flag; determining that a pps_ref_wraparound_enabled_flag is set; and receiving a init_qp_minus26 value. 9. The method of claim 6, wherein receiving, by the decoder, arranged syntax elements in the PPS level comprises: receiving, by the decoder, the arranged syntax elements in the PPS level, wherein the arranged syntax elements in the PPS level are arranged by: receiving a rpl1_idx_present_flag flag; receiving a pps_weighted_pred_flag flag; receiving a pps_weighted_bipred_flag flag; receiving a pps_ref_wraparound_enabled_flag flag; determining that pps_ref_wraparound_enabled_flag flag is equal to 1; receiving a pps_pic_width_minus_wraparound_offset value; determining that pps_ref_wraparound_enabled_flag is not equal to 1; and setting a pps_pic_width_minus_wraparound_offset value; and receiving a init_qp_minus26 value. 10. A method for decoding a video signal, comprising: receiving, by the decoder, arranged syntax elements in sequence parameter set (SPS) level so that inter prediction related syntax elements are grouped in versatile video coding (VVC) syntax at a coding level; obtaining, at the decoder, a first reference picture and a second reference picture associated with a video block in a bitstream, wherein the first reference picture ^(^) is before a current picture and the second reference picture is after the current picture in display order; obtaining, at the decoder, first prediction samples of the video block from a reference block in the first reference picture wherein i and j represent a coordinate of one sample with the current picture; obtaining, at the decoder, second prediction samples of the video block from a reference block in the second reference picture and obtaining, at the decoder, bi-prediction samples based on the arranged syntax elements in the SPS level, the first prediction samples and the second prediction samples 11. The method of claim 10, wherein receiving, by the decoder, the arranged syntax elements in the SPS level comprises: receiving, by the decoder, the arranged syntax elements in the SPS level, wherein the arranged syntax elements in the SPS level are arranged by: determining that a sps_transform_skip_enabled_flag flag is set; receiving a sps_weighted_pred_flag flag; setting a num_ref_pic_lists_in_sps value; setting a sps_log2_diff_min_qt_min_cb_inter_slice value; determining that a sps_max_mtt_hierarchy_depth_inter_slice value is not equal to 0; receiving a sps_ref_wraparound_enabled_flag flag; receiving a sps_mmvd_enabled_flag flag; determining that a sps_affine_enabled_flag flag is set; receiving a sps_bcw_enabled_flag flag; determining that a MaxNumMergeCand value is greater than 2; setting a log2_parallel_merge_level_minus2 value; and receiving a sps_isp_enabled_flag flag. 12. The method of claim 10, wherein receiving, by the decoder, the arranged syntax elements in the SPS level comprises: receiving, by the decoder, the arranged syntax elements in the SPS level, wherein the arranged syntax elements in the SPS level are arranged by: determining that a sps_transform_skip_enabled_flag flag is set; receiving a sps_weighted_pred_flag flag; determining a sps_video_parameter_set_id flag is greater than 0; setting a num_ref_pic_lists_in_sps value; receiving a sps_ref_wraparound_enabled_flag flag; receiving a sps_mmvd_enabled_flag flag; determining the sps_mmvd_enabled_flag flag is set; receiving a sps_affine_enabled_flag flag; determining that the sps_affine_enabled_flag flag is set; receiving a sps_bcw_enabled_flag flag; determining that a MaxNumMergeCand value is greater than equal to 2; setting a log2_parallel_merge_level_minus2 value; and receiving a sps_isp_enabled_flag flag. 13. A computing device, comprising: one or more processors; and a non-transitory computer-readable storage medium storing instructions executable by the one or more processors, wherein the one or more processors are configured to: receive arranged syntax elements in sequence parameter set (SPS) level, wherein the arranged syntax elements in the SPS level are arranged so that functions of related syntax elements are grouped in versatile video coding (VVC) syntax at a coding level; receive, in response to multiple syntax elements satisfy a predefined condition, a second syntax element immediately after the multiple syntax elements; and perform a related syntax element function to video data from a bitstream in accordance with the multiple syntax elements and the second syntax element. 14. The computing device of claim 13, wherein the functions of related syntax elements comprise intra tools, inter tools, screen content tools, transform tools, quantization tools, loop filter tools, and partition tools. 15. The computing device of claim 13, wherein the one or more processors configured to receive the arranged syntax elements in the SPS level are further configured to: receive the arranged syntax elements in the SPS level, wherein the arranged syntax elements in the SPS level are arranged by: receive a sps_mmvd_enabled_flag value; determine that sps_mmvd_enabled_flag flag is equal to 1; receive a sps_fpel_mmvd_enabled_flag value; determine that sps_mmvd_enabled_flag flag is not equal to 1; and set a sps_fpel_mmvd_enabled_flag value. 16. The computing device of claim 13, wherein the one or more processors configured to receive the arranged syntax elements in the SPS level are further configured to: receive the arranged syntax elements in the SPS level, wherein the arranged syntax elements in the SPS level are arranged by: determine that sps_transform_skip_enabled_flag is set; receive a sps_mip_enabled_flag flag; determine that ChromaArrayType value is not equal to 0; receive a sps_cclm_enabled_flag flag; determine that chroma_format_idc value is equal to 1; receive a sps_chroma_horizontal_collocated_flag flag; receive a sps_chroma_vertical_collocated_flag flag; receive a sps_weighted_pred_flag flag; set a num_ref_pic_lists_in_sps value; set a sps_log2_diff_min_qt_min_cb_inter_slice value; determine that sps_max_mtt_hierarchy_depth_inter_slice value is not equal to 0; set a sps_log2_diff_max_bt_min_qt_inter_slice value; receive a sps_ref_wraparound_enabled_flag flag; set a six_minus_max_num_merge_cand value; determine that sps_affine_enabled_flag flag is set; determine that sps_mmvd_enabled_flag flag is set; set a log2_parallel_merge_level_minus2 value; and determine that sps_mts_enabled_flag flag is set. 17. The computing device of claim 13, wherein the one or more processors configured to receive the arranged syntax elements in the SPS level are further configured to: receive the arranged syntax elements in the SPS level, wherein the arranged syntax elements in the SPS level are arranged by: determine that a sps_transform_skip_enabled_flag is set; receive a sps_mip_enabled_flag flag; determine that a ChromaArrayType value is not equal to 0; determine that a chroma_format_idc value is equal to 1; receive a sps_palette_enabled_flag flag; determine that a sps_max_mtt_hierarchy_depth_inter_slice value is not equal to 0; receive a sps_ref_wraparound_enabled_flag flag set a six_minus_max_num_merge_cand value; determine that a sps_affine_enabled_flag flag is set; set a log2_parallel_merge_level_minus2 value; and receive a sps_mts_enabled_flag flag. 18. The computing device of claim 13, wherein the one or more processors are further configured to: receive arranged syntax elements in picture parameter set (PPS) level so that functions of related syntax elements are grouped in VVC syntax at a coding level. 19. The computing device of claim 18, wherein the one or more processors configured to receive the arranged syntax elements in the SPS level are further configured to: receive the arranged syntax elements in the PPS level, wherein the arranged syntax elements in the PPS level are arranged by: determine that a pps_cu_chroma_qp_offset_list_enabled_flag flag is set; set a num_ref_idx_default_active_minus1 value; receive a pps_weighted_pred_flag flag; receive a rpl_info_in_ph_flag flag; receive a wp_info_in_ph_flag flag; determine that a pps_ref_wraparound_enabled_flag flag is set; and receive a deblocking_filter_control_present_flag flag. 20. The computing device of claim 18, wherein the one or more processors configured to receive the arranged syntax elements in the PPS level are further configured to: receive the arranged syntax elements in the PPS level, wherein the arranged syntax elements in the PPS level are arranged by: receive a rpl1_idx_present_flag flag; receive a pps_weighted_pred_flag flag; receive a wp_info_in_ph_flag flag; determine that a pps_ref_wraparound_enabled_flag is set; and receiving a init_qp_minus26 value. 21. The computing device of claim 18, wherein the one or more processors configured to receive the arranged syntax elements in the PPS level are further configured to: receive the arranged syntax elements in the PPS level, wherein the arranged syntax elements in the PPS level are arranged by: receive a rpl1_idx_present_flag flag; receive a pps_weighted_pred_flag flag; receive a pps_ref_wraparound_enabled_flag flag; determine that the pps_ref_wraparound_enabled_flag flag is set; set a pps_pic_width_minus_wraparound_offset value; and receiving a init_qp_minus26 value. 22. A non-transitory computer-readable storage medium storing a plurality of programs for execution by a computing device having one or more processors, wherein the plurality of programs, when executed by the one or more processors, cause the computing device to perform acts comprising: receiving, by the decoder, arranged syntax elements in sequence parameter set (SPS) level so that inter prediction related syntax elements are grouped in versatile video coding (VVC) syntax at a coding level; obtaining, at the decoder, a first reference picture and a second reference picture associated with a video block in a bitstream, wherein the first reference picture is before a current picture and the second reference picture ^ is after the current picture in display order; obtaining, at the decoder, first prediction samples of the video block from a reference block in the first reference picture wherein i and j represent a coordinate of one sample with the current picture; obtaining, at the decoder, second prediction samples of the video block from a reference block in the second reference picture and obtaining, at the decoder, bi-prediction samples based on the arranged syntax elements in the SPS level, the first prediction samples and the second prediction samples 23. The non-transitory computer-readable storage medium of claim 22, wherein the plurality of programs further cause the computing device to perform: receiving, by the decoder, the arranged syntax elements in the SPS level, wherein the arranged syntax elements in the SPS level are arranged by: determining that a sps_transform_skip_enabled_flag flag is set; receiving a sps_weighted_bipred_flag flag; setting a num_ref_pic_lists_in_sps value; setting a sps_log2_diff_min_qt_min_cb_inter_slice value; determining that a sps_max_mtt_hierarchy_depth_inter_slice value is not equal to 0; receiving a sps_ref_wraparound_enabled_flag flag; receiving a sps_mmvd_enabled_flag flag; determining that a sps_affine_enabled_flag flag is set; receiving a sps_bcw_enabled_flag flag; determining that a MaxNumMergeCand value is greater than 2; setting a log2_parallel_merge_level_minus2 value; and 12receiving a sps_isp_enabled_flag flag. 24. The non-transitory computer-readable storage medium of claim 22, wherein the plurality of programs further cause the computing device to perform: receiving, by the decoder, the arranged syntax elements in the SPS level, wherein the arranged syntax elements in the SPS level are arranged by: determining that a sps_transform_skip_enabled_flag flag is set; receiving a long_term_ref_pics_flag flag; determining a sps_video_parameter_set_id flag is greater than 0; setting a num_ref_pic_lists_in_sps value; receiving a sps_ref_wraparound_enabled_flag flag; receiving a sps_mmvd_enabled_flag flag; determining the sps_mmvd_enabled_flag flag is set; receiving a sps_affine_enabled_flag flag; determining that the sps_affine_enabled_flag flag is set; receiving a sps_bcw_enabled_flag flag; determining that a MaxNumMergeCand value is greater than equal to 2; setting a log2_parallel_merge_level_minus2 value; and receiving a sps_isp_enabled_flag flag. |
Table 3. NAL unit type codes and NAL unit type classes [0052] VVC inherits the parameter set concept of HEVC with a few modification and additions. Parameter sets can be either part of the video bitstream or can be received by a decoder through other means (including out-of-band transmission using a reliable channel, hard coding in encoder and decoder, and so on). A parameter set contains an identification, which is referenced, directly or indirectly, from the slice header as discussed in more detail later. The referencing process is known as “activation.” Depending on the parameter set type, the activation occurs per picture or per sequence. The concept of activation through referencing was introduced, among other reasons, because implicit activation by virtue of the position of the information in the bitstream (as common for other syntax elements of a video codec) is not available in case of out-of-band transmission. [0053] The video parameter set (VPS) was introduced to convey information that is applicable to multiple layers as well as sub-layers. The VPS was introduced to address these shortcomings as well as to enable a clean and extensible high-level design of multilayer codecs. Each layer of a given video sequence, regardless of whether they have the same or different sequence parameter sets (SPS), refer to the same VPS. The syntax of the video parameter set in current VVC draft specification is illustrated in Table 4. How to read the Table 4 is illustrated in the appendix section of this disclosure which could also be found in the VVC specification. Table 4. Video parameter set RBSP syntax
[0054] In VVC, SPSs contain information which applies to all slices of a coded video sequence. A coded video sequence starts from an instantaneous decoding refresh (IDR) picture, or a BLA picture, or a CRA picture that is the first picture in the bitstream and includes all subsequent pictures that are not an IDR or BLA picture. A bitstream consists of one or more coded video sequences. The content of the SPS can be roughly subdivided into six categories: 1) a self-reference (its own ID); 2) decoder operation point related information (profile, level, picture size, number sub-layers, and so on); 3) enabling flags for certain tools within a profile, and associated coding tool parameters in case the tool is enabled; 4) information restricting the flexibility of structures and transform coefficient coding; 5) temporal scalability control; and 6) visual usability information (VUI), which includes HRD information. The syntax and the associated semantic of the sequence parameter set in current VVC draft specification is illustrated in Table 5 and Table 6, respectively. How to read the Table 5 is illustrated in the appendix section of this disclosure which could also be found in the VVC specification. Table 5. Sequence parameter set RBSP syntax Table 6. Sequence parameter set RBSP semantics [0055] VVC’s picture parameter set (PPS) contains such information which could change from picture to picture. The PPS includes information roughly comparable what was part of the PPS in HEVC, including: 1) a self-reference; 2) initial picture control information such as initial quantization parameter (QP), a number of flags indicating the use of, or presence of, certain tools or control information in the slice header; and 3) tiling information. The syntax and the associated semantic of the picture parameter set in current VVC draft specification is illustrated in Table 7 and Table 8, respectively. How to read the Table 7 is illustrated in the appendix section of this disclosure which could also be found in the VVC specification. Table 7. Picture parameter set RBSP syntax Table 8. Picture parameter set RBSP semantics [0056] The slice header contains information that can change from slice to slice, as well as such picture related information that is relatively small or relevant only for certain slice or picture types. The size of slice header may be noticeably bigger than the PPS, particular when there are tile or wavefront entry point offsets in the slice header and RPS, prediction weights, or reference picture list modifications are explicitly signaled. The syntax of the picture header in current VVC draft specification is illustrated in Table 10. How to read the Table 10 is illustrated in the appendix section of this disclosure which could also be found in the VVC specification. Table 10. Picture header structure syntax [0057] Improvements to Syntax Elements [0058] In current VVC, when there are similar syntax elements for intra and inter prediction, respectively, in some places the syntax elements related to inter prediction are defined prior to those related to intra prediction. Such an order may not be preferable, given that fact that intra prediction is allowed in all picture/slice types while inter prediction is not. It would be beneficial from standardization point of view to always define intra prediction related syntaxes prior to those for inter prediction. [0059] It is also observed that in current VVC, some syntax elements that are highly correlated to each other are defined at different places in a spread manner. It would be also beneficial from standardization point of view to group some syntaxes together. [0060] Proposed Methods In this disclosure, to address the issues as pointed out in the “problem statement” section, methods are provided to simplify and/or further improve the existing design of the high-level syntax. It is noted that the invented methods could be applied independently or jointly. [0061] Grouping the Partition Constraint Syntax Elements by Prediction Type [0062] In this disclosure, it is proposed to rearrange the syntax elements so that the intra prediction related syntax elements are defined before those related to inter prediction. According to the disclosure, the partition constraint syntax elements are grouped by prediction type, with intra prediction related first, followed by inter prediction related. In one embodiment, the order of the partition constraint syntax elements in SPS is consistent with the order of the partition constraint syntax elements in the picture header. An example of the decoding process on VVC Draft is illustrated in Table 11 below. The changes to the VVC Draft are shown using the bold and italicized font while the deleted parts are shown in strikethrough font. Table 11. Proposed sequence parameter set RBSP syntax [0063] Grouping the dual-tree chroma syntax elements [0064] In this disclosure, it is proposed to group the syntax elements related to dual-tree chroma type. In one embodiment, the partition constraint syntax elements for dual-tree chroma in SPS should be signaled together under dual-tree chroma cases. An example of the decoding process on VVC Draft is illustrated in Table 12 below. The changes to the VVC Draft are shown using the bold and italicized font while the deleted parts are shown in strikethrough font. Table 12. Proposed sequence parameter set RBSP syntax
[0065] If also considering defining intra prediction related syntaxes prior to those related to inter prediction, according to the method of the disclosure, another example of the decoding process on VVC Draft is illustrated in Table 13 below. The changes to the VVC Draft are shown using the bold and italicized font while the deleted parts are shown in strikethrough font. Table 13. Proposed sequence parameter set RBSP syntax
[0066] Conditionally signaling inter-prediction related syntax elements [0067] As mentioned in the earlier description, according to the current VVC, intra prediction is allowed in all picture/slice types while inter prediction is not. According to this disclosure, it is proposed to add a flag in VVC syntax at certain coding level to indicate whether inter prediction is allowed or not in a sequence, picture and/or slice. In case inter prediction is not allowed, inter prediction related syntaxes are not signaled at the corresponding coding level, e.g. sequence, picture and/or slice level. [0068] According to this disclosure, it is also proposed to add a flag in VVC syntax at certain coding level to indicate whether inter slices such as P-slice and B-slice are allowed or not in a sequence, picture and/or slice. In case inter slices are not allowed, inter slices related syntaxes are not signaled at the corresponding coding level, e.g. sequence, picture and/or slice level. [0069] Some examples are given based on the proposed inter slices allowed flags in the following section. And, the proposed inter prediction allowed flags can be used in a similar way. [0070] When the proposed inter slice allowed flags are added at different levels. These flags can be signaled in a hierarchical manner. When the signaled flag at higher level indicates that inter slice is not allowed, the flag at lower levels has no need to be signaled and can be inferred as 0 (which mean inter slice is not allowed). [0071] In one example, according to the method of the disclosure, a flag is added in SPS to indicate if inter slice is allowed in coding the current video sequence. In case it is not allowed, inter slice related syntax elements are not signaled in SPS. An example of the decoding process on VVC Draft is illustrated in Table 14 below. The changes to the VVC Draft are shown using the bold and italicized font while the deleted parts are shown in strikethrough font. It is noted that there are syntax elements other than those introduced in the example. For example, there are many inter slice (or inter prediction tools) related syntax elements such as sps_weighted_pred_flag, sps_temporal_mvp_enabled_flag, sps_amvr_enabled_flag, sps_bdof_enabled_flag and so on; there are also syntax elements related to the reference picture lists such as long_term_ref_pics_flag, inter_layer_ref_pics_present_flag, sps_idr_rpl_present_flag and so on. All these syntax elements related to inter prediction can selectively be controlled by the proposed flag. Table 14. Proposed sequence parameter set RBSP syntax [0072] 7.4.3.3 Sequence parameter set RBSP semantics [0073] sps_inter_slice_allowed_flag equal to 0 specifies that all coded slices of the video sequence have slice_type equal to 2 (which indicates that the coded slice is I slice). sps_inter_slice_allowed_flag equal to 1 specifies that there may or may not be one or more coded slices in the video sequence that have slice_type equal to 0 (which indicates that the coded slice is P slice) or 1 (which indicates that the coded slice is B slice). [0074] In another example, according to the method of the disclosure, a flag is added in picture parameter set PPS to indicate if inter slice is allowed in coding the pictures associated with this PPS. In case it is not allowed, the selected inter prediction related syntax elements are not signaled in PPS. [0075] In yet another example, according to the method of the disclosure, the inter slice allowed flags can be signaled in a hierarchical manner. A flag is added in SPS to indicate if inter slice is allowed in coding the pictures associated with this SPS e.g. sps_inter_slice_allowed_flag. When sps_inter_slice_allowed_flag is equal to 0 (which means inter slice is not allowed), the inter slice allowed flag in picture header can be omitted for signaling and be inferred as 0. An example of the decoding process on VVC Draft is illustrated in Table 15 below. The changes to the VVC Draft are shown using the bold and italicized font while the deleted parts are shown in strikethrough font. Table 15. Proposed sequence parameter set RBSP syntax [0076] 7.4.3.7 Picture header structure semantics [0077] ph_inter_slice_allowed_flag equal to 0 specifies that all coded slices of the picture have slice_type equal to 2. ph_inter_slice_allowed_flag equal to 1 specifies that there may or may not be one or more coded slices in the picture that have slice_type equal to 0 or 1. When not present, the value of ph_inter_slice_allowed_flag is inferred to be equal to 0. [0078] Grouping the inter-related syntax elements [0079] In this disclosure, it is proposed to rearrange the syntax elements so that the inter prediction related syntax elements are grouping in VVC syntax at certain coding level, e.g. sequence, picture and/or slice level. According to the disclosure, it is proposed to rearrange the syntax elements related to inter slices in the sequence parameter set (SPS). An example of the decoding process on VVC Draft is illustrated in Table 16 below. The changes to the VVC Draft are shown using the bold and italicized font while the deleted parts are shown in strikethrough font. Table 16. Proposed sequence parameter set RBSP syntax [0080] Another example of the decoding process on VVC Draft is illustrated in Table 17 below. The changes to the VVC Draft are shown using the bold and italicized font while the deleted parts are shown in strikethrough font. Table 17. Proposed sequence parameter set RBSP syntax [0081] In yet another example, the decoding process on VVC Draft is illustrated in Table 18 below. The changes to the VVC Draft are shown using the bold and italicized font while the deleted parts are shown in strikethrough font. Table 18. Proposed sequence parameter set RBSP syntax [0082] In yet another example, the decoding process on VVC Draft is illustrated in Table 19 below. The changes to the VVC Draft are shown using the bold and italicized font while the deleted parts are shown in strikethrough font. Table 19. Proposed sequence parameter set RBSP syntax [0083] FIG. 4 shows a method for decoding a video signal in accordance with the present disclosure. The method may be, for example, applied to a decoder. [0084] In step 410, the decoder may receive, through a bitstream, arranged syntax elements in sequence parameter set (SPS) level. The arranged syntax elements in the SPS level may be arranged so that functions of related syntax elements are grouped in versatile video coding (VVC) syntax at a coding level. [0085] In step 412, the decoder may receive, through the bitstream and in response to multiple syntax elements satisfy a predefined condition, a second syntax element immediately after the multiple syntax elements. The multiple syntax elements, for example, may include a sps_mmvd_enabled_flag flag and a sps_fpel_mmvd_enabled_flag flag. The predefined condition, for example, may include sps_mmvd_enabled_flag flag being equal to 1. [0086] In step 414, the decoder may perform, through the bitstream, a related syntax element function to video data from the bitstream in accordance with the multiple syntax elements and the second syntax element. [0087] According to this disclosure, it is also proposed to add a flag in VVC syntax at certain coding level to indicate whether inter slices such as P-slice and B-slice are allowed or not in a sequence, picture and/or slice. In case inter slices are not allowed, inter slices related syntaxes are not signaled at the corresponding coding level, e.g. sequence, picture and/or slice level. In one example, according to the method of the disclosure, a flag, sps_inter_slice_allowed_flag, is added in SPS to indicate if inter slice is allowed in coding the current video sequence. In case it is not allowed, inter slice related syntax elements are not signaled in SPS. An example of the decoding process on VVC Draft is illustrated in Table 20 below. The added parts are shown using the bold and italicized font while the deleted parts are shown in strikethrough font. Table 20. Proposed sequence parameter set RBSP syntax [0088] Another example of the decoding process on VVC Draft is illustrated in Table 21 below. The changes to the VVC Draft are shown using the bold and italicized font while the deleted parts are shown in strikethrough font. Table 21. Proposed sequence parameter set RBSP syntax [0089] Grouping the similar function syntax elements [0090] In this disclosure, it is proposed to rearrange the syntax elements so that the similar function, e.g. intra tools, inter tools, screen content tools, transform tools, quantization tools, loop filter tools and/or partition tools, related syntax elements are grouping in VVC syntax at certain coding level, e.g. sequence, picture and/or slice level. According to the disclosure, it is proposed to rearrange the syntax elements in the sequence parameter set (SPS) so that the similar function related syntax elements are grouping. An example of the decoding process on VVC Draft is illustrated in Table 23 below. The changes to the VVC Draft are shown using the bold and italicized font while the deleted parts are shown in strikethrough font. Table 23. Proposed sequence parameter set RBSP syntax [0091] Another example of the decoding process on VVC Draft is illustrated in Table 24 below. The changes to the VVC Draft are shown using the bold and italicized font while the deleted parts are shown in strikethrough font. Table 24. Proposed sequence parameter set RBSP syntax [0092] According to the disclosure, it is proposed to rearrange the syntax elements in the picture parameter set (PPS) so that the similar function related syntax elements are grouped. An example of the decoding process on VVC Draft is illustrated in Table 25 below. The changes to the VVC Draft are shown using the bold and italicized font while the deleted parts are shown in strikethrough font. Table 25. Proposed sequence parameter set RBSP syntax [0093] Another example of the decoding process on VVC Draft is illustrated in Table 26 below. The changes to the VVC Draft are shown using the bold and italicized font while the deleted parts are shown in strikethrough font. Table 26. Proposed sequence parameter set RBSP syntax
[0094] In yet another example, the decoding process on VVC Draft is illustrated in Table 27 below. The changes to the VVC Draft are shown using the bold and italicized font while the deleted parts are shown in strikethrough font. Table 27. Proposed sequence parameter set RBSP syntax [0095] FIG. 5 shows a method for decoding a video signal in accordance with the present disclosure. The method may be, for example, applied to a decoder. [0096] In step 510, the decoder may receive arranged syntax elements in SPS level so that inter prediction related syntax elements are grouped in VVC syntax at a coding level. [0097] In step 512, the decoder may obtain a first reference picture and a second reference picture associated with a video block in a bitstream. The first reference picture is before a current picture and the second reference picture ^ is after the current picture in display order. [0098] In step 514, the decoder may obtain first prediction samples of the video block from a reference block in the first reference picture . The i and j represent a coordinate of one sample with the current picture. [0099] In step 516, the decoder may obtain second prediction samples of the video block from a reference block in the second reference picture [00100] In step 518, the decoder may obtain bi-prediction samples based on the arranged syntax elements in the SPS level, the first prediction samples and the second prediction samples [00101] FIG. 6 shows a method for decoding a video signal in accordance with the present disclosure. The method may be, for example, applied to a decoder. [00102] In step 610, the decoder may receive a bitstream that includes VPS, SPS, PPS, picture header, and slice header for coded video data. [00103] In step 612, the decoder may decode the VPS. [00104] In step 614, the decoder may decode the SPS and obtain an arranged partition constraint syntax elements in SPS level. [00105] In step 616, the decoder may decode the PPS. [00106] In step 618, the decoder may decode the picture header. [00107] In step 620, the decoder may decode the slice header. In step 622, the decoder may decode the video data based on VPS, SPS, PPS, picture header and slice header. [00108] The above methods may be implemented using an apparatus that includes one or more circuitries, which include application specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, micro-controllers, microprocessors, or other electronic components. The apparatus may use the circuitries in combination with the other hardware or software components for performing the above described methods. Each module, sub-module, unit, or sub-unit disclosed above may be implemented at least partially using the one or more circuitries. [00109] FIG.7 shows a computing environment 710 coupled with a user interface 760. The computing environment 710 can be part of a data processing server. The computing environment 710 includes processor 720, memory 740, and I/O interface 750. [00110] The processor 720 typically controls overall operations of the computing environment 710, such as the operations associated with the display, data acquisition, data communications, and image processing. The processor 720 may include one or more processors to execute instructions to perform all or some of the steps in the above-described methods. Moreover, the processor 720 may include one or more modules that facilitate the interaction between the processor 720 and other components. The processor may be a Central Processing Unit (CPU), a microprocessor, a single chip machine, a GPU, or the like. [00111] The memory 740 is configured to store various types of data to support the operation of the computing environment 710. Memory 740 may include predetermine software 742. Examples of such data include instructions for any applications or methods operated on the computing environment 710, video datasets, image data, etc. The memory 740 may be implemented by using any type of volatile or non-volatile memory devices, or a combination thereof, such as a static random access memory (SRAM), an electrically erasable programmable read-only memory (EEPROM), an erasable programmable read-only memory (EPROM), a programmable read-only memory (PROM), a read-only memory (ROM), a magnetic memory, a flash memory, a magnetic or optical disk. [00112] The I/O interface 750 provides an interface between the processor 720 and peripheral interface modules, such as a keyboard, a click wheel, buttons, and the like. The buttons may include but are not limited to, a home button, a start scan button, and a stop scan button. The I/O interface 750 can be coupled with an encoder and decoder. [00113] In some embodiments, there is also provided a non-transitory computer-readable storage medium comprising a plurality of programs, such as comprised in the memory 740, executable by the processor 720 in the computing environment 710, for performing the above- described methods. For example, the non-transitory computer-readable storage medium may be a ROM, a RAM, a CD-ROM, a magnetic tape, a floppy disc, an optical data storage device or the like. [00114] The non-transitory computer-readable storage medium has stored therein a plurality of programs for execution by a computing device having one or more processors, where the plurality of programs when executed by the one or more processors, cause the computing device to perform the above-described method for motion prediction. In some embodiments, the computing environment 710 may be implemented with one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), graphical processing units (GPUs), controllers, micro-controllers, microprocessors, or other electronic components, for performing the above methods. [00115] Other examples of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed here. This application is intended to cover any variations, uses, or adaptations of the disclosure following the general principles thereof and including such departures from the present disclosure as come within known or customary practice in the art. It is intended that the specification and examples be considered as exemplary only. [00116] It will be appreciated that the present disclosure is not limited to the exact examples described above and illustrated in the accompanying drawings, and that various modifications and changes can be made without departing from the scope thereof.
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