| JPH04115727 | PULSE OUTPUT CIRCUIT |
| JPS5295151 | WAVEFORM SHAPING CIRCUIT |
| US4053795A | 1977-10-11 |
| 1. | an electronic comparator circuit adapted for implementation as an integrated circuit semiconductor device comprising: a first differential amplifier adapted for connection to an incoming data source to be compared; a sourcefollower 'stage connected to said first differential amplifier for buffering its output to enable it to be broad banded; and a second differential amplifier connected to said sourcefollower stage for handling large signal swings while providing additional gain to the output from said first differential amplifier; and a third cascoded gain stage connected to said second differential amplifier to provide increased circuit gain with a railtorail output. |
| 2. | The comparator circuit as described in Claim 1 including pushpull means interconnecting said second differ¬ ential amplifier and said third gain stage for minimizing power required for the third gain stage. |
| 3. | The comparator circuit as described in Claim 1 including diode clamping means in said first differential amplifier for limiting the voltage excursion at its output node thereby keeping it in the saturation region of operation for a longer period of time so. that it can recover faster from relatively large variations in input signals. |
| 4. | The comparator circuit as described in Claim 1 wherein all of the transistor elements of said circuit are MOSFET devices connected between common power lines. OMPI . |
| 5. | An electronic comparator for receiving, comparing and amplifying relatively small signals in a data stream comprising: a first differential amplifier having a plurality of MOSFE 's including one input MOSFET with its gate connected to a data input source and another input MOSFET with its gat connected to ground, a single current control MOSFET and a pair of load MOSFET's in series with said input MOSFET's, an a pair of clamping diodes connected to nodes between said in put and said load devices, including an output node; a sourcefollower stage connected to said first diffe ential amplifier for buffering its output to enable it to be broad banded; and a second differential amplifier connected to said sourcefollower stage for handling large signal swings while providing additional gain to the output from said first differential amplifier; and a third cascoded gain stage connected to said second differential amplifier to provide increased circuit gain wit a railtorail output. |
| 6. | The comparator as described in Claim 5 wherein sa sourcefollower stage is comprised of a pair of MOSFET devic in series, one of which has its gate connected to a said nod of said first differential amplifier and the other of which has its gate connected to a source of bias voltage and to th gate of said current control MOSFET. |
| 7. | The comparator as described in Claim 5 wherein sa cascoded gain stage comprises three MOSFET devices connected in series including a first said device for limiting the sig nal swing and thus the capacitance of this gain stage. OivTP r. |
Background of the Invention
This invention relates to an improved comparator circuit particularly adaptable for implementation as an integrated circuit device using complementary metal-oxide-silicon (CMOS) technology.
Comparators have long been used extensively as building blocks in electronic circuits for the purpose of comparing and amplifying the difference between two signal sources, as for example, in analog to digital conversion circuits- Often this difference between two signal sources is required to be sensed at a very rapid rate. Such speed requirements became especially difficult to obtain in the attempted implementation of compara¬ tor circuits as part of larger integrated circuit devices where the difference in the signal values is small. Previous attempts to achieve relatively high * speed are described, for example, in IEEE Journal of Solid State Operation Circuits, Feb. 1979, pp. 38-46, and Memorandum No. UCB/ERL M78/27 24 May 1978, College of Engineering, University of California, Berkeley, CA, Page 128. However, such circuits as disclosed therein require a relatively large amount of integrated circuit "chip" area and also large amounts of power. In providing a comparator as part of a monolithic integrated circuit, such as a "codec" for use in digital transmission, such excessive requirements for chip area and power are not desirable. The present invention solves this problem.
It is therefore one object of the present invention to provide an improved comparator circuit particularly adaptable for implementation as an integrated circuit device.
Another object of the invention is to provide a compara¬ tor which has a high resolution capability with high speed, ( e.g., a comparator capable of resolving less than 300 yV in less than 2 μsecs.)
Still another object of the invention is to provide a comparator having good common mode rejection characteristics which is an important criteria ' for high resolution systems .
Another object of the invention is to provide a compa or with, relatively low power dissipation using Class A-B dr for the output.
Brief Summary of the Invention
A comparator according to the principles of the prese invention comprises a CMOS circuit consisting of four stages The first stage is an input preamplifier in the form of a di ferential amplifier which receives the two data inputs to be compared. Connected to this differential amplifier is a sou follower stage that provides a low impedance output which dr another differential amplifier. This second differential am fier drives another cascoded gain stage using a push-pull dr The input preamplifier is a high gain, broad banded stage th serves to deliver, with speed, a relatively large signal to succeeding gain stages which in turn are designed to respond rapidly to large signal stimuli. The broadbanding is achiev By the source followers which buffer the input capacitance o elements from the second differential amplifier. Diode clam is used to force the preamplifier to remain in the saturatio region to provide adequate gain during operation with relati small signal input data and also a relatively fast response the input stage.
Other objects, advantages and features of the inventi may become apparent from the following detailed description one preferred embodiment presented in conjunction with the accompanying drawing.
Brief Description of the Drawing
The single figure is a circuit diagram of a comparato embodying principles of the present invention.
Detailed Description of Embodiment
With reference to the drawing, a circuit diagram is shown for a comparator 10 embodying principles of the presen invention which are particularly adapted for implementation
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part of a monolithic integrated circuit semiconductor device. In broad terms, the circuit comprises a first differential amplifier section 12 which is essentially an input preamplifier that receives the two voltage inputs to be compared. Connected to the amplifier section 12 is a source-follower stage 14 which supplies inputs to a second differential amplifier section 16. The latter is connected through a push-pull network 18 to a third cascoded gain stage 20 that provides the circuit output.
All of the aforesaid circuit components may be comprised of MOSFET elements as part of a monolithic integrated circuit structure. Thus, as shown, all circuit elements are connected between V and V power leads 22 and 24. The first differen¬ tial amplifier 12 is comprised of a constant current MOSFET 26 having one source/drain terminal connected to the line 24 and its other terminal connected to a lead 28 that also intercon¬ nects one source/drain terminal for each of a pair of signal input MOSFET' s 30 and 32. The gate of MOSFET 30 is connected via lead 34 to a data input source for the voltage signals to be compared, and the gate of MOSFET 32 is connected by a lead 36 to ground. The other terminals of MOSFET's 30 and 32 are connected by a pair of leads 38 and 40 to the terminals of another pair of MOSFET's 42 and 44. The other terminal of each of these latter MOSFET's is connected to the power lead 22 and their gates are interconnected by a lead 46. A lead 48 from this latter lead extends to the interconnecting lead 38 between MOSFET's 30 and 42. In two separate leads extending between leads 38 and 40 are two clamping diodes 50 and 52 which are important to the operation of he circuit.
The source-follower stage 14 comprises a first pair of MOSFET devices 54 and 56 connected in series between the power leads 22 and 24 and a second pair of MOSFET devices 58 and 60 that are similarly connected. The gate of MOSFET 54 is con¬ nected to a junction 62 in the lead 38 of the first differen¬ tial amplifier which is also the junction for one end of the interconnecting lead from diode 50. The other end of the lead from diode 50 is connected to a junction 64 in the interconnec¬ ting lead 40. This latter junction is also connected to the
gate of the source-follower MOSFET 58. The gate of MOSFET 5 is supplied with a bias, voltage and is connected to the _gate of the differential amplifier MOSFET 26 whose gate in turn i also connected to source-follower MOSFET 60.
The source-follower MOSFET's 54 and 56 are interconne ted by a lead 66 and the MOSFET 1 s 58 and 60 are similarly in connected by a lead 68. Connected to and extending from the leads 66 and 68 is a pair of leads 70 and 72 respectively, extending to the gates of a pair of MOSFET' s 74 and 76. The latter MOSFET' s are the input devices for the second differe tial amplifier 16. One source/drain terminal of these latte MOSFET's is interconnected by a lead 78 which is connected t one terminal of a MOSFET 80 whose other terminal is connecte to the V power line 24. The gate of MOSFET 80 is connecte to the gate of the source-follower device 60. Connected to the MOSFET's 74 and' 76 by a pair of leads 82 and 84 respecti is another pair of MOSFET's 86 and .88. The other terminals these latter devices are connected to the power line 22 and their gates are interconnected by a lead 90 which is connect by a lead 92 to a junction 94 in the lead 82.
As described above, the second differential amplifier is connected to a push-pull network comprised of a pair of MOSFET' s 96 and 98 connected in series between the power lea 22 and 24. The gate of MOSFET 96 is connected to a lead 100 from an output junction 102 in the lead 84 of the second dif ential amplifier. The gate of MOSFET 98 is connected to the lead 104 which is also connected to the gate of MOSFET's 26, 60 and 80. The two MOSFET's 9*6 and 98 are interconnected by lead 106 and an output junction 108 therein is connected to gate of a MOSFET 110 of the cascoded gain stage 20 for the comparator 10.
The latter gain stage also includes MOSFET's 112 and which are connected in series with MOSFET 110 between the po leads 22 and 24. The gate of MOSFET 112 is connected to the lead 100 from the second differential amplifier 16 and the g of MOSFET 114 is connected to ground. The MOSFET ' s 110 and are interconnected by a lead 116, having a junction 118 whic provides the output of the circuit.
In operation, when power is supplied across the leads 22 and 24, all of the circuit elements are "on" and ready to operate. An input signal is applied to the gate of MOSFET 34 and MOSFET 32's gate is grounded. This causes the difference of the input signals to be amplified by the first differential amplifier at its junction 64. The function of the diodes 50 and 52 is to clamp node 64 within a diode drop of node 62. This limits the voltage excursion of node 6 and thus keeps the first differential stage in the saturation region of oper¬ ation longer. Thus, this stage can recover faster from the linear region of operation, for example, when a large differ¬ ential input signal was present on its input and is then pre¬ sented with small differential input signals of the opposite polarity.
The output of the differential amplifier drives the source-follower MOSFET's 54, 56, 5 " 8 and 60. The source- followers buffer the first differential stage from the input capacitance of the second differential stage. The input capa¬ citance of the second differential stage can be large due to Miller multiplication of the gate drain overlap capacitance of MOSFET's. Thus, the source-followers 14 serve to "broadband" the first gain stage or differential amplifier 12 providing increased circuit speed.
The output of the source-followers directly drive the input MOSFET's 74 and 76 of second gain stage or differential amplifier 16. This stage does not require diode clamping since it is designed to handle large voltage swings. This stage drives the final gain stage. The final gain stage is' a cascoded stage. This reduces the input capacitance of this stage and thus broadbands the second differential gain stage.
The cascode stage is accomplished by MOSFET's 112, 114, and 110. MOSFET 114 limits the signal swing and thus gain on the node between MOSFET's 112 and 114. This reduces the input capacitance of this gain stage. The push-pull MOSFET's 96 and 98 are connected between the second and third gain stages so that power is conserved by causing the third gain stage MOSFET's 14 and 15 to operate in Class A-B mode (i.e., when 96 tends to turn on, 98 tends to turn off and vice versa.)
In summary, it is seen that the comparator circuit 1 operates to receive. nd compare relatively, small signals which are amplified by stages which allow relatively large input signal swings. Thus, the circuit has a wide range of performance that can be applied to a variety of uses; and i also comprises relatively few components that can be compac arranged in an integrated circuit semiconductor device.
In one embodiment of the comparator according to thi invention an overall g 3 ain of 125 dB was achieved with 25 MH unit gain bandwidth. Compared with prior art capacitor circuits, this is a relatively high gain for a large bandwi
To those skilled in the art to which this invention relates, many changes in construction and widely differing embodiments and applications of the invention will suggest themselves without departing from the spirit and scope of t invention. The disclosures and the description herein are purely illustrative and are not intended to be in any sense limiting.
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