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Title:
HIGH-RESOLUTION FET VDS ZERO-VOLT-CROSSING TIMING DETECTION SCHEME
Document Type and Number:
WIPO Patent Application WO/2018/200843
Kind Code:
A1
Abstract:
In methods and apparatus for detecting zero-volt crossing in a field-effect transistor, a comparator (200) compares a drain-to source voltage (Vds) of the transistor to a threshold voltage (VTH-ds). A gate voltage signal (Vgs) of the transistor is provided to a clock input of the comparator (200), such that the gate voltage signal (Vgs) is used to latch a result of the comparison to an output of the comparator (200). A control function with respect to the transistor is performed based on the value of the comparator (200) output.

Inventors:
XU, Jingwei (5801 Furneaux Dr, Plano, TX, 75093, US)
DEVARAJAN, Vijayalakshmi (7505 Higgins Lane, Plano, TX, 75024, US)
ZHANG, Gangqiang (3709 Stoneway Dr, Plano, TX, 75025, US)
PEREIRA, Angelo William (6509 Renewal Rd, Plano, TX, 75074, US)
Application Number:
US2018/029609
Publication Date:
November 01, 2018
Filing Date:
April 26, 2018
Export Citation:
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Assignee:
TEXAS INSTRUMENTS INCORPORATED (P.O. Box 655474, Mail Station 3999Dallas, TX, 75265-5474, US)
TEXAS INSTRUMENTS JAPAN LIMITED (24-1, Nishi-shinjuku 6-chomeShinjuku-k, Tokyo ., 160-8366, JP)
International Classes:
H03K5/153; H03K17/13
Foreign References:
US20100327947A12010-12-30
US20150145565A12015-05-28
US7330065B22008-02-12
Attorney, Agent or Firm:
DAVIS, Michael A. Jr. et al. (Texas Instruments Incorporated, P.O. Box 655474 Mail Station 399, Dallas Texas, 75265-5474, US)
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Claims:
CLAIMS

What is claimed is:

1. A control module for controlling a field-effect transistor having a gate, a drain and a source, the control module comprising:

a comparator operable to receive the drain-to-source voltage of the transistor and compare it to a threshold voltage, the comparator comprising a clock input operable to receive a gate voltage of the transistor, wherein the received gate voltage is used to latch a result of the comparison to an output of the comparator; and

control circuitry operable to receive the comparator output and to perform a control function with respect to the transistor based on the value of the comparator output.

2. The control module of claim 1 wherein the comparator comprises:

a first output configured to provide an on-late flag indicative of whether the gate voltage turned the transistor on before or after the drain-to-source voltage went from high to low, wherein a rising edge of the received gate voltage is used to latch a result of the comparison to the first output of the comparator; and

a second output configured to provide an off-late flag indicative of whether the gate voltage turned the transistor off before or after the drain-to-source voltage went from low to high, wherein a falling edge of the received gate voltage is used to latch a result of the comparison to the second output of the comparator.

3. The control module of claim 2 wherein the control circuitry is operable to perform at least one control function with respect to the transistor based on the value of the on-late flag and the value of the off-late flag.

4. The control module of claim 3 wherein the control circuitry is operable to adjust the timing of the rising edge of a gate driver signal driving the transistor based on the value of the on-late flag, and to adjust the timing of the falling edge of the gate driver signal based on the value of the off-late flag.

5. The control module of claim 3 wherein the control circuitry is operable to adjust the timing of the rising edge of a pulse-width modulation (PWM) signal used to generate a gate driver signal driving the transistor based on the value of the on-late flag, and to adjust the timing of the falling edge of the PWM signal based on the value of the off-late flag.

6. The control module of claim 5 wherein the control circuitry is operable to average the value of the on-late flag over a plurality of PWM cycles and to average the value of the off-late flag over a plurality of PWM cycles, and to adjust the timing of the rising edge of the PWM signal based on the average value of the on-late flag and to adjust the timing of the falling edge of the PWM signal based on the average value of the off-late flag.

7. A control module for controlling a field-effect transistor having a gate, a drain and a source, the control module comprising:

a drain-to-source voltage comparator operable to receive the drain-to-source voltage (Vds) of the transistor and compare it to a VdS threshold, the Vds comparator having at least one output configured to provide a Vds edge transition signal indicative of VdS crossing the VdS threshold; a gate-to- source voltage comparator operable to receive the gate-to- source voltage (Vgs) of the transistor and compare it to a Vgs threshold, the Vgs comparator having at least one output configured to provide a Vgs edge transition signal indicative of Vgs crossing the Vgs threshold; and

at least one latching element having a data input, a clock input, and an output, the data input operably coupled to receive a VdS edge transition signal from the VdS comparator and the clock input operably coupled to receive a Vgs edge transition signal from the Vgs comparator such that the Vgs edge transition signal serves to latch the VdS edge transition signal to the latch output.

8. The control module of claim 7 further comprising a delay-matching module operably coupled to receive the VdS edge transition signal from the VdS comparator and the Vgs edge transition signal from the Vgs comparator, apply a matching delay to at least one of the VdS edge transition signal and the Vgs edge transition signal to compensate for any disparity in delays inherent in the VdS comparator and the Vgs comparator, and to provide a delay-adjusted Vds edge transition signal to the data input of the at least one latching element and a delay-adjusted Vgs edge transition signal to the clock input of the at least one latching element.

9. The control module of claim 7 further comprising control circuitry operable to receive the output of the at least one latching element and to perform a control function with respect to the transistor based on the value of the output of the at least one latching element.

10. The control module of claim 7 wherein the at least one latching element comprises at least one D flip-flop.

11. The control module of claim 7 wherein:

the Vds comparator comprises first and second outputs, the first output configured to provide a VdS rising-edge signal indicative of VdS rising above the VdS threshold, the second output configured to provide a VdS falling-edge signal indicative of VdS falling below the VdS threshold; and

the VgS comparator comprises first and second outputs, the first output configured to provide a Vgs rising-edge signal indicative of Vgs rising above the Vgs threshold, the second output configured to provide a Vgs falling-edge signal indicative of Vgs falling below the Vgs threshold.

12. The control module of claim 11 wherein the at least one latching element comprises: a first latching element having a data input, a clock input, and an output, the data input operably coupled to receive the VdS falling-edge signal from the VdS comparator and the clock input operably coupled to receive the Vgs rising-edge signal from the Vgs comparator such that the Vgs rising-edge signal serves to latch the VdS falling-edge signal to the latch output, the latch output thus serving as an on-late flag indicative of whether the Vgs signal turned the transistor on before or after the drain-to-source voltage went from high to low; and

a second latching element having a data input, a clock input, and an output, the data input operably coupled to receive the VdS rising-edge signal from the VdS comparator and the clock input operably coupled to receive the Vgs falling-edge signal from the Vgs comparator such that the Vgs falling-edge signal serves to latch the VdS rising-edge signal to the latch output, the latch output thus serving as an off-late flag indicative of whether the Vgs signal turned the transistor off before or after the drain-to-source voltage went from low to high.

13. The control module of claim 12 further comprising control circuitry operable to receive the on-late flag and the off-late flag and to perform at least one control function with respect to the transistor based on the value of the on-late flag and the value of the off-late flag.

14. The control module of claim 12 further comprising:

a first delay-matching element operable to apply a matching delay to the Vds rising-edge signal to compensate for any disparity in delays inherent in the VdS comparator and the Vgs comparator, and to provide a delay-adjusted VdS rising-edge signal to the data input of the second latching element;

a second delay-matching element operable to apply a matching delay to the Vds falling- edge signal to compensate for any disparity in delays inherent in the VdS comparator and the Vgs comparator, and to provide a delay-adjusted VdS falling-edge signal to the data input of the first latching element;

a third delay-matching element operable to apply a matching delay to the Vgs falling-edge signal to compensate for any disparity in delays inherent in the VdS comparator and the Vgs comparator, and to provide a delay-adjusted Vgs falling-edge signal to the clock input of the second latching element; and

a fourth delay-matching element operable to apply a matching delay to the Vgs rising- edge signal to compensate for any disparity in delays inherent in the VdS comparator and the Vgs comparator, and to provide a delay-adjusted Vgs rising-edge signal to the clock input of the first latching element.

15. A method of controlling a field-effect transistor, comprising:

comparing, with a comparator, a drain-to source voltage of the transistor to a threshold voltage;

providing a gate voltage signal of the transistor to a clock input of the comparator such that the gate voltage signal is used to latch a result of the comparison to an output of the comparator; and

performing a control function with respect to the transistor based on the value of the comparator output.

16. The method of claim 15 further comprising:

providing, at a first output of the comparator, an on-late flag indicative of whether the gate voltage signal turned the transistor on before or after the drain-to-source voltage went from high to low;

providing, at a second output of the comparator, an off-late flag indicative of whether the gate voltage signal turned the transistor off before or after the drain-to-source voltage went from low to high;

latching a result of the comparison to the first output of the comparator in response to receiving a rising edge of the gate voltage signal at the clock input; and

latching a result of the comparison to the second output of the comparator in response to receiving a falling edge of the gate voltage signal at the clock input.

17. The method of claim 16 wherein the performing a control function comprises performing at least one control function with respect to the transistor based on the value of the on-late flag and the value of the off-late flag.

18. The method of claim 17 wherein the performing a control function comprises adjusting the timing of the rising edge of a gate driver signal driving the transistor based on the value of the on-late flag and adjusting the timing of the falling edge of the gate driver signal based on the value of the off-late flag.

19. The method of claim 18 wherein the performing a control function comprises adjusting the timing of the rising edge of a pulse-width modulation (PWM) signal used to generate a gate driver signal driving the transistor based on the value of the on-late flag and adjusting the timing of the falling edge of the PWM signal based on the value of the off-late flag.

20. The method of claim 19 wherein the performing a control function comprises averaging the value of the on-late flag over a plurality of PWM cycles, averaging the value of the off-late flag over a plurality of PWM cycles, adjusting the timing of the rising edge of the PWM signal based on the average value of the on-late flag, and adjusting the timing of the falling edge of the PWM signal based on the average value of the off-late flag.

Description:
HIGH-RESOLUTION FET VDS ZERO- VOLT-CROSSING TIMING DETECTION SCHEME

BACKGROUND

[0001] In a zero-volt switching (ZVS) scheme, a field-effect transistor (FET) delivering power to a load is switched on or off only when the drain-source voltage is at or near zero volts. ZVS uses pulse width modulation (PWM), but with an additional separate phase to the PWM timing to allow for ZVS operation. Zero-volt switching enables the voltage regulator to engage in "soft switching," thus avoiding the switching losses that are typically incurred during conventional PWM operation and timing.

[0002] ZVS is useful in a variety of power conversion systems that require high switching frequencies at higher input voltages and voltage drops. Wireless power transfer and charging systems are an example of a technology that can benefit greatly from zero-volt switching. The Alliance For Wireless Power (A4WP) is an industry standard group that uses the principles of magnetic resonance to develop a wireless energy transfer system over distance. A4WP wireless power transfer uses directed and controlled magnetic fields to replace traditional power cords. To do this, the transmitter has one or more primary windings to induce an even magnetic field above its surface. A receiver in the magnetic field has a secondary winding to capture the magnetic energy and convert it back to electrical energy. In A4WP wireless power transfer, the switching frequencies are multiples of 6.78MHz. Accurate zero-voltage crossing (ZVC) detection is a starting point for high efficiency ZVS control. With such high-frequency switching, the timing accuracy of the zero-volt switching needs to be on the order of a nanosecond. Conventional zero-voltage crossing detection methods employ very fast comparators and gate drivers that have very little delay. However, typical comparator delay is already above the aforementioned nanosecond range.

SUMMARY

[0003] In described examples of a control module for controlling a field-effect transistor, the control module includes a comparator and control circuitry. The comparator receives the drain-to-source voltage of the transistor and compares it to a threshold voltage. The comparator has a clock input that receives a gate voltage of the transistor, such that the received gate voltage is used to latch a result of the comparison to an output of the comparator. The control circuitry receives the comparator output and performs a control function with respect to the transistor based on the value of the comparator output.

[0004] In other described examples of a control module for controlling a field-effect transistor, the control module includes a drain-to-source voltage comparator, a gate-to-source voltage comparator, and at least one latching element. The drain-to- source voltage comparator receives the drain-to-source voltage (Vds) of the transistor and compares it to a i s threshold. The Vd S comparator has at least one output configured to provide a Vi s edge transition signal indicative of Vds crossing the Vd S threshold. The gate-to- source voltage comparator receives the gate-to- source voltage (V gs ) of the transistor and compares it to a V gs threshold. The V gs comparator has at least one output configured to provide a V gs edge transition signal indicative of V g s crossing the V gs threshold. The at least one latching element has a data input, a clock input, and an output. The data input is operably coupled to receive a Vd S edge transition signal from the Vds comparator, and the clock input is operably coupled to receive a V gs edge transition signal from the V gs comparator, such that the V gs edge transition signal serves to latch the Vd S edge transition signal to the latch output.

[0005] In a method of controlling a field-effect transistor, a comparator compares a drain-to-source voltage of the transistor to a threshold voltage. A gate voltage signal of the transistor is provided to a clock input of the comparator, such that the gate voltage signal is used to latch a result of the comparison to an output of the comparator. A control function with respect to the transistor is performed based on the value of the comparator output.

BRIEF DESCRIPTION OF THE DRAWINGS

[0006] FIG. 1 is a schematic block diagram of an illustrative wireless power transfer system.

[0007] FIG. 2 is a functional block diagram of a comparator for use in a zero-volt switching detection circuit in accordance with illustrative embodiments.

[0008] FIG. 3 is a timing diagram demonstrating timing relationships between the Vds signal, the Vgs signal, the ON LATE flag, and the OFF LATE flag in accordance with illustrative embodiments.

[0009] FIG. 4 is a functional block diagram of a comparator system capable of implementing a comparator, such as the comparator described with respect to FIG. 2 in accordance with illustrative embodiments.

[0010] FIG. 5 is a timing diagram timing showing timing relationships for various signals in a comparator system, such as that shown in FIG. 4 in accordance with illustrative timing and control schemes.

[0011] FIG. 6 is a flowchart of a method of controlling a field-effect transistor in accordance with illustrative embodiments.

DETAILED DESCRIPTION OF EXAMPLE EMB ODFMENT S

[0012] Illustrative aspects are directed to techniques for achieving accurate and efficient zero-volt crossing detection in a high-frequency zero-volt-switching system. For purposes of illustration, the zero-volt-crossing detection methods are described herein with respect to an A4WP wireless power transfer and charging system. However, aspects of example embodiments are applicable to substantially any system that employs zero-volt switching.

[0013] FIG. 1 is a schematic block diagram of an illustrative wireless power transfer system 100. The primary side 105 of the wireless power transfer system 100 includes a primary-side control module 110, which illustratively comprises an integrated circuit controller. The primary-side control module 110 generates control signals and provides them to external switches Ql, Q2, Q3 and Q4. In the illustrative embodiment shown in FIG. 1, the switches Ql, Q2, Q4 and Q4 are metal-oxide-semiconductor field-effect transistors (MOSFETs) and the control signals provided by the primary-side control module 110 are gate-driver signals. The junction of switches Ql and Q3 define a tank node Nl, and the junction of switches Q2 and Q4 define a tank node N2. Specifically, in the illustrative embodiment of FIG. 1, tank node Nl is defined by the junction of the source of transistor Ql and the drain of transistor Q3. Tank node N2 is defined by the junction of the source of transistor Q2 and the drain of transistor Q4. The drains of transistors Ql and Q2 are coupled to an input voltage Vi n . The sources of transistors Q3 and Q4 are coupled to ground. Tank nodes Nl and N2 are coupled to a primary-side LC tank circuit comprising primary-side capacitor C pr imary and primary-side inductor L pr imary- The tank node Nl is coupled to a first terminal of primary-side capacitor C pr imary. The primary-side inductor L pr imary is coupled between the second terminal of capacitor Cprimary and tank node N2.

[0014] Primary-side inductor Lprimary is inductively coupled across air gap M to secondary-side inductor L seC ondary- On the secondary side 115 of the wireless power transfer system 100, an LC tank circuit comprising secondary-side inductor L seC ondary and secondary-side capacitor C se condary is coupled to tank nodes N3 and N4. The tank node N3 is coupled to a first terminal of the secondary-side inductor L secondar y. The secondary-side capacitor C seC ondary is coupled between the second terminal of inductor L seC ondary and tank node N4. A secondary-side control module 120, which in an illustrative embodiment comprises an integrated circuit controller, generates control signals and provides them to external switches Q5, Q6, Q7 and Q8 arranged in an H-bridge configuration. In illustrative embodiments, the primary-side control module 110 and the secondary-side control module 120 are part of a single integrated circuit. In the illustrative embodiment shown in FIG. 1, the switches Q5, Q6, Q7 and Q8 are MOSFETs and the control signals provided by the secondary-side control module 120 are gate-driver signals. The junction of switches Q5 and Q7 define tank node N3, and the junction of switches Q6 and Q8 define tank node N4. Specifically, in the illustrative embodiment of FIG. 1, tank node N3 is defined by the junction of the source of transistor Q5 and the drain of transistor Q7. Tank node N4 is defined by the junction of the source of transistor Q6 and the drain of transistor Q8. The sources of transistors Q7 and Q8 are coupled to ground. The drains of transistors Q5 and Q6 define an output node NO that provides an output voltage V BRID G E OU T -

[0015] In illustrative embodiments, an integrated phase-locked loop (PLL) (not shown) locks onto an external high-frequency crystal oscillator (also not shown). The phase-locked loop is illustratively integrated on the same integrated circuit as the primary-side control module 110 and the secondary-side control module 120. The primary-side control module 110 includes a digital pulse-width modulation (PWM) generation state machine that works in tandem with the phase-locked loop to generate the driving waveforms that drive four gate-driver circuits in the primary-side control module 110. The four gate-driver circuits, in turn, drive the gates of the primary-side transistors Ql, Q2, Q3 and Q4 and the series LC resonant tank to transmit power across the air gap M. On the secondary side 115, the recovered signal captured across the resonator capacitor C seC ondary 1S sliced to generate the digital reference signal for the phase-locked loop. The secondary-side control module 120 includes a PWM generation state machine seeks to drive the gates of the transistors Q5, Q6, Q7 and Q8 of the secondary-side H-bridge for synchronous rectification. To maximize efficiency on the primary side 105 and the secondary side 115, it is important to optimize the switching times for the transistors Q1-Q8. Zero-volt switching (ZVS) is an effective means of optimizing these switching times. Precise zero-volt crossing (ZVC) detection is crucial for maximizing the efficiency of a ZVS scheme.

[0016] A zero-volt switching event determines the turn-on event of each of the primary-side transistors Q1-Q4. The turn-off edge is conveniently synced to the reference clock, which sets up the timing reference of the whole system. On the secondary side 115, the timing reference is based on the current waveform I P through the primary-side inductor vrimary^ The secondary-side control module 120 performs synchronous rectification that emulates a full bridge diode rectifier. Zero-volt switching conditions are detected for both turn-on and turn-off edges of the secondary-side transistors Q5-Q8.

[0017] To illustrate aspects of switching control in accordance with example embodiments, the operation and control of transistor Ql is described hereinbelow. This description regarding transistor Ql also pertains to the other primary-side transistors Q2-Q4 and, in many respects, the secondary-side transistors Q5-Q8. The drain-to-source voltage signal Vd S of transistor Ql is complex due to the ringing generated by the bond wires of the transistor. The additional voltage resulting from L pr i ma r y (dlp/dt) can be greater than Id S Rds ZVS detection circuit in the primary-side control module 110 detects if the Vd S of the corresponding transistor Ql is above or below a predetermined threshold V-m-ds- In an illustrative embodiment, the ZVS detection circuit includes a comparator that compares Vd S to the predetermined threshold V-m-ds- FIG. 2 is a functional block diagram of a comparator 200 for use in such a ZVS detection circuit in accordance with illustrative aspects. In illustrative embodiments, a comparator such as the comparator 200 of FIG. 2 corresponds to each of the external transistors Q1-Q8. Ideally, the threshold V-m-ds would be set at 0 V. But in an illustrative embodiment, V-m-ds is set at a value which is still reasonably close to ZVS condition, but relatively immune to parasitic effects, such as 1 V. The gate-to- source voltage V gs of the transistor is used as a clock to latch the comparator output. The comparator 200 has two outputs, which are referred to herein as ON LATE and OFF LATE. The latched outputs, ON LATE and OFF LATE, indicate whether the switching edge is early or late relative to ZVS condition. The primary-side control module 105 uses the ON LATE and OFF LATE flags to adjust the timing control of the gate-driver signal provided to transistor Ql to minimize the delay between the transistor switching time and the Vd S zero-crossing time. The flags are illustratively used by the PWM state machine to generate desired switching waveforms. In illustrative embodiments, both the ON LATE and OFF LATE signals are averaged over multiple (such as eight) PWM cycles to obtain the average value over a longer time period and thereby reduce noise sensitivity. It is again noted that, while this switching control scheme is described with respect to transistor Ql, the same or similar principles apply to the other primary-side transistor Q2-Q4 and to the secondary-side transistors Q5-Q8.

[0018] When the V gs signal transitions from low to high, as indicated by the V gs crossing a gate-to- source threshold voltage Vm- g s, the result of the comparison of the V dS signal to the drain-to-source threshold voltage V-m- d s is latched to the ON LATE output of the comparator 200. If the drain-to-source voltage V dS is less than the threshold voltage when the V gs signal goes high (thereby latching the comparator output) ; the ON LATE output signal becomes (or remains) 1 (logic-high), indicating that the gate-driver signal went high (turning the transistor Ql on) after the V d s signal dropped to zero. Thus, the gate-driver signal turned the transistor Ql on late. If, on the other hand, the drain-to-source voltage V dS is still greater than the threshold voltage when the V g s signal goes high, the ON LATE output signal becomes (or remains) 0 (logic-low), indicating that the gate-driver signal went high before the V dS signal dropped to zero. Note that the V d s signal can change earlier than, or later than, the gate-driver signal switches the transistor on or off due to the effects of current driven through the LC tank circuit by the associated load. In either case, V dS will become low before V gs becomes high. For maximum switching efficiency, it is desirable that the gate-driver signal (and therefore the V gs signal) goes high and the V d s signal goes low as close to simultaneously as possible.

[0019] When the V gs signal transitions from high to low, the result of the comparison of the V d s signal to the threshold voltage V-m- d s is latched to the OFF LATE output of the comparator 200. If the drain-to-source voltage V dS starts to rise and crosses the threshold voltage V-m- d s immediately after the V gs signal goes low (thereby latching the comparator output) , the OFF LATE output signal becomes (or remains) 1 (logic-high), indicating that the gate-driver signal held the transistor Ql on and kept V dS low, otherwise the LC tank circuit would have driven V dS high (to its off-state voltage level). Thus, the gate-driver signal turned the transistor Ql off late. If, on the other hand, the drain-to-source voltage V dS does not immediately rise when the V gs signal goes low, the OFF LATE output signal becomes 0 (logic-low), indicating that the gate-driver signal went low before the V dS signal dropped to zero. For maximum switching efficiency, it is desirable that the gate-driver signal (and therefore the V gs signal) goes low and the V dS signal goes high as close to simultaneously as possible.

[0020] FIG. 3 is a timing diagram demonstrating illustrative timing relationships between the V d s signal, the V gs signal, the ON LATE flag, and the OFF LATE flag. For purposes of demonstrating the use of the V gs signal to latch the V dS comparator, the timing diagram of FIG. 3 represents an ideal system without taking into account various system delays that exist in real- world systems. Such delays are described and accounted for hereinbelow. As described hereinabove, the gate-to- source voltage V gs is used to latch the outputs of the comparator 200. When the V gs signal goes high, the result of the comparison of the drain-to-source voltage V dS to the threshold voltage V-m- d s is latched to the ON LATE output. At a time ti in FIG. 3, the V gs signal goes high, by virtue of the gate-driver signal provided by the primary-side control module 110 (or, for secondary-side transistors Q5-Q8, by the secondary-side control module). As shown in FIG. 3, at time ti, the drain-to- source voltage V dS has already dropped below the comparator threshold voltage V-m- d s, which in the illustrative embodiment of FIG.3 is shown to be approximately IV. Thus V dS is less than V-m- d s and the ON_LATE flag goes high, indicating that the gate-driver signal turned the transistor on late, i.e., after the V dS signal has already gone low.

[0021] As described hereinabove, when the V gs signal goes low, the result of the comparison of the drain-to-source voltage V dS to the threshold voltage V-m- d s is latched to the OFF LATE output. At a time t 2 in FIG. 3, the V gs signal goes low, by virtue of the gate-driver signal provided by the primary-side control module 110 (or, for secondary-side transistors Q5-Q8, by the secondary-side control module). As shown in FIG. 3, at time t 2 , the drain-to-source voltage V d s starts to rise and crosses the threshold voltage V-m- d s immediately after the V gs signal goes low. Thus the OFF LATE flag goes high, indicating that the gate-driver signal turned the transistor off late.

[0022] At a time t 3 in FIG. 3, the V gs signal goes high again. As shown in FIG. 3, at time t 3 , the drain-to-source voltage V dS is still greater than the threshold voltage V-m, and therefore the ON LATE flag goes low, indicating that the gate-driver signal turned the transistor on early, i.e., before the V dS signal has gone low. At a time in FIG. 3, the V gs signal goes low again. At time t 3 , the drain-to-source voltage V d s is still less than the threshold voltage V-m, and therefore the OFF LATE flag goes low, indicating that the gate-driver signal turned the transistor off early, i.e., before the V dS signal has gone high.

[0023] In illustrative embodiments, a PWM state machine in the primary-side control module 110 uses the latched outputs from the V dS comparators corresponding to each of the primary-side transistors Q1-Q4 to regulate control bits to the phase-locked loop. Similarly, a PWM state machine in the secondary-side control module 120 uses the latched outputs from the V dS comparators corresponding to each of the secondary-side transistors Q5-Q8 to regulate control bits to the phase-locked loop. The PWM state machines employ control algorithms that seek to obtain locking positions for the rising and falling edges of the gate-driver waveforms. These algorithms illustratively employ an initial pulse-width value for the gate-driver waveforms. For example, in an illustrative embodiment, the hard-coded values for the initial pulse widths at the beginning of the search algorithm are set to -40% DC on the primary side and -10% DC on the secondary side. During operation, the pulse widths are then adjusted dynamically based on the values of the ON LATE and OFF LATE flags (illustratively averaged over multiple PWM cycles) to maximize the alignment of the Vd S and V gs signals.

[0024] In an illustrative embodiment, the primary-side PWM state machine and the secondary- side PWM state machine each first seeks to lock the rising edge of the gate-driver waveform to the ON LATE flag. This is done by successively shifting the position of the rising edge of the gate-driver signal until the ON LATE flag changes state. In illustrative embodiments, the time period between position changes is programmable via non-volatile memory (NVM) and can be tuned based on the bandwidth requirements of the system. The PWM state machine next repeats the process for the falling edge. The PWM state machine performs this process with respect to all four external transistors (transistors Q1-Q4 for the primary-side PWM state machine and transistors Q5-Q8 for the secondary-side PWM state machine). When both the rising and falling edges for all four external transistors have attained optimal positions for zero-volt switching, the state machine toggles the edges around those positions.

[0025] FIG. 4 is a functional block diagram of a comparator system 400 that implements a comparator such as the comparator 200 described with respect FIGS. 2 and 3 in accordance with illustrative embodiments. The comparator system 400 implements the timing control scheme, described with respect to FIGS. 2 and 3, whereby the V gs signal is used as a clock signal controlling the latching of the outputs of the comparator 200 (or the outputs of the comparator system 400). The comparator system 400 also accounts for some of the above-described timing delays in a real-world system. As shown in FIG. 4, the comparator system 400 actually employs two comparators - a Vd S comparator 410 and a V gs comparator 420. Vd S comparator 410 receives the drain-to-source voltage Vd S and compares it to the predetermined threshold Vm-ds- As described with respect to FIG. 2, ideally, the threshold V-m-ds would be set at 0 V. But in an illustrative embodiment, V-m-ds is set at a value, such as 1 V, which is still reasonably close to ZVS condition, but relatively immune to parasitic effects. The V dS comparator 410 has two outputs, referred to herein as RISE P and FALL P. The RISE P output responds to the rising edge of the Vd S signal by going high when the Vd S signal rises above the voltage threshold V-m-ds- The FALL P output responds to the falling edge of the V dS signal by going high when the V dS signal drops below the voltage threshold V-m-ds-

[0026] V gS comparator 420 receives the gate-to-source voltage V dS and compares it to a predetermined value that corresponds to the turn-on threshold voltage of the associated transistor. In an illustrative embodiment, the V gs input of the V gs comparator 420 is coupled directly to the gate-up and gate-down pins of the gate-driver circuit. The Vg s comparator 420 has two outputs, referred to herein as ON CLK and OFF CLK. The ON CLK output responds to the rising edge of the V dS signal by going high when the V gs signal rises above the voltage threshold Vm-gs- The OFF CLK output responds to the falling edge of the V dS signal by going high when the V gs signal drops below the voltage threshold Vm-gs-

[0027] The V dS comparator 410 and V gs comparator 420 are both subject to an inherent amount of delay. Accordingly, an inherent amount of delay exists between the time that the V dS signal changes state (i.e., rises above, or drops below, the voltage threshold V-m-ds) and the time that the corresponding V dS output (RISE P or FALL P) changes state (i.e., goes high or goes low). Likewise, an inherent amount of delay exists between the time that the V gs signal changes state (i.e., rises above, or drops below, the voltage threshold V TH - g s) and the time that the corresponding V dS output changes state. The amount of delay introduced by the V dS comparator 410 and V gs comparator 420 can vary from part to part, and also in response to process variance. The delay matching/trimming module 430 includes circuitry that accounts for and adjusts for these inherent delays. Each of the outputs of both the V dS comparator 410 and the V gs comparator 420 are provided to a delay element in the delay matching/trimming module 430. Specifically, the RISE P signal is provided to delay element 435, the FALL P signal is provided to delay element 440, the OFF CLK signal is provided to delay element 445, and the ON CLK signal is provided to delay element 450. Each of the delay elements 435-450 also includes a trim input (not shown) for receiving a trim value that dictates an amount of delay that is to be introduced by the corresponding delay element. These trim values can be determined during or after manufacture by various methods that can include testing. In an illustrative embodiment, the trim values are stored in non-volatile memory. In this way, the delay matching/trimming module 430 can compensate for the delays inherent in the V dS comparator 410 and V gs comparator 420. In illustrative embodiments, the delay matching/trimming module 430 also compensates for the delay that exists between the time that the PWM signal controlling the gate-driver circuit changes state and the time that the gate voltage changes in response thereto.

[0028] The delay matching/trimming module 430 thus produces delay-adjusted versions of the signals received from the V dS comparator 410 and V gs comparator 420. Specifically, delay element 435 outputs a signal referred to herein as RISE P DLY, delay element 440 outputs a signal referred to herein as FALL P DLY, delay element 445 outputs a signal referred to herein as OFF CLK DLY, and delay element 450 outputs a signal referred to herein as ON CLK DLY.

[0029] The output latches and averaging logic module 460 receives the delay-adjusted outputs of the V ds comparator 410 and V gs comparator 420 from the delay matching/trimming module 430. The output latches and averaging logic module 460 implements the latching of the outputs of the V ds comparator 410 at times dictated by the rising and falling edges of the V gs signal as represented by the outputs of the V gs comparator 420. In the illustrative embodiment represented by FIG. 4, the latching of the ON LATE and ON LATE flags is implemented using two D flip- flops 465 and 470. D flip-flop 470 receives the FALL P DLY signal from the delay matching/trimming module 430 at its D input and receives the ON.CLK.DLY signal at its clock input. Thus, when the ON CLK DLY signal goes high, indicating that the gate-to-source voltage V gs has gone high, the value existing at the D input, i.e., the value of the FALL P DLY signal, is latched to the output Q as the ON LATE flag. This value will be a digital 1 (logic- high) if the Vds voltage dropped below the Vd S threshold Vm-ds before the V gs signal rose above the V gs threshold Vm- gs - In other words, ON LATE = 1 indicates that the transistor turned on "late," i.e., after the drain-to-source voltage dropped below its threshold Vm- ds - [0030] D flip-flop 465 receives the RISE P DLY signal from the delay matching/trimming module 430 at its D input and receives the OFF.CLK.DLY signal at its clock input. Thus, when the OFF CLK DLY signal goes high, indicating that the gate-to- source voltage V gs has gone low, the value existing at the D input, i.e., the value of the RISE P DLY signal, is latched to the output Q as the OFF LATE flag. This value will be a digital 1 (logic-high) if the V dS voltage rose above the Vd S threshold V-m-ds before the V gs signal dropped below the V gs threshold Vm-gs- In other words, OFF LATE = 1 indicates that the transistor turned off "late," i.e., after the drain- to-source voltage rose above its threshold V-m-ds-

[0031] As described hereinabove with respect to FIGS. 2 and 3, the PWM state machines of the primary-side control module 110 and secondary-side control module 120 use the ON LATE and OFF LATE flags to generate desired switching waveforms, such as by iteratively adjusting, based on those ON LATE and OFF LATE flags, the positions of the rising and falling edges of the PWM signals used to generate the gate driver signals that are provided to transistors Q1-Q8. In illustrative embodiments, the output latches and averaging logic module 460 includes averaging logic that serves to average the ON LATE and OFF LATE signals over multiple (for example, eight) PWM cycles to obtain the average value over a longer time period and thereby reduce noise sensitivity.

[0032] FIG. 5 is a timing diagram timing showing timing relationships for various signals in a comparator system such as comparator system 400 of FIG. 4 in accordance with illustrative timing and control schemes. The timing diagram of FIG. 5 shows the PWM control signal, the gate-to-source voltage V gs , the drain-to-source voltage V dS , the ON_CLK signal, the ON CLK DLY signal, the FALL P signal, the FALL P DLY signal, and the ON LATE flag. These signals are described hereinabove with respect to FIG. 4. The PWM/V gs plot shows both the pulse-width modulation signal PWM and the gate-to-source voltage V gs . The PWM signal is illustratively generated by the pulse-width-modulation state machine and provided to the gate- driver circuit, which generates a gate-driver signal based on the PWM signal. The gate-to- source voltage Vg s is representative of the gate-driver signal provided to the gate of the transistor by the gate-driver circuit. At a time ti in FIG. 5, the PWM signal goes high. After a driver delay 500, the gate-to- source voltage V gs crosses the transistor turn on threshold V-m-g s , which in the illustrative embodiment of FIG. 5, is 2.5V, at a time t 2 . After a V gs comparator delay 510, the ON CLK output of the V gs comparator 420 goes high at a time U in response to the V gs signal crossing the V-m-g s threshold at time t 2. At a time t 3 , the drain-to-source voltage V dS of the transistor crosses the drain-to-source voltage threshold V-m- ds , which in the illustrative embodiment of FIG. 5 is set at 1 V. After a V dS comparator delay 520, the FALL P output of the V ds comparator 410 goes high at a time t 5 in response to the V dS signal crossing the V-m- ds threshold at time t 3.

[0033] As shown in FIG. 5, a delay mismatch exists between the V gs comparator delay 510 and the V ds comparator delay 520. Accordingly, in the illustrative example of FIG. 5, the V gs comparator 420 is subject to a longer delay than the V dS comparator 410. The delay matching/trimming module 430 compensates for this delay mismatch by performing delay matching on the ON CLK and FALL P signals. Specifically, the delay elements 440 and 450 apply a delay to the FALL P and ON CLK signals, respectively. The amount of delay applied is defined by the trim value that is supplied to the delay elements 440 and 450. The trim values are based on the amount of delay that is inherent in each of the comparators 410 and 420 as determined, illustratively, during and after manufacture via testing and other means. The output of delay element 440, referred to as FALL P DLY, constitutes the delay-adjusted version of the FALL P signal, and the output of delay element 450, referred to as ON CLK DLY, constitutes the delay-adjusted version of the ON CLK signal. In accordance with the implemented delay adjustments, the FALL P DLY signal goes high at a time t 6 and the ON CLK DLY signal goes high at a time t 7 . The FALL P DLY signal is provided to the D-flip-flop 470 of the output latches and averaging logic module 460, and the ON CLK DLY signal is provided to the clock input of D flip-flop 470. Thus when the ON CLK DLY signal goes high at time t 7 , the value at the D input is latched to the Q output of the flip-flop, which provides the ON LATE flag. Because the FALL P DLY signal is high at time t 7 , the ON LATE flag goes accordingly. Due to a small delay inherent in the D flip-flop 460, the ON LATE goes high at time t 8 , reflecting the fact that the V gs signal went high, thereby turning the transistor on, late (i.e., after the drain-to-source voltage V dS dropped below the V-m-ds)-

[0034] FIG. 6 is a flowchart of a method of controlling a field-effect transistor in accordance with illustrative embodiments. At block 600, a comparator compares a drain-to source voltage of the transistor to a threshold voltage. At block 610, a gate voltage signal of the transistor is provided to a clock input of the comparator such that the gate voltage signal is used to latch a result of the comparison to an output of the comparator. At block 620, a control function with respect to the transistor is performed based on the value of the comparator output.

[0035] Modifications are possible in the described embodiments, and other embodiments are possible, within the scope of the claims. For example, described embodiments include a zero-volt-crossing detection scheme performed by a V dS comparator that uses the gate voltage of the transistor as a clock input to latch the comparator output, but other variations are possible. Also, for example, described embodiments include a wireless power transfer system using zero-volt switching, but other systems may likewise use zero-volt switching.