Technical Field

The present invention relates to high-speed electronic switches and, in particular, to a CMOS switch characterized by low resistance in its electrically conductive ("ON") state and by very low propagation delay times.

Background of the Invention The following background information is presented with reference to interface circuitry for a microprocessor emulator and its target circuit. To achieve reliable emulation, it is often necessary to provide _, buffer switches for all signals at the point of interface between a microprocessor emulator probe and the target system circuitry. There are many points within the emulator itself at which data and command signals must be switched in response to microprocessor and target system stimuli. Because the speed of microprocessor operation has been increasing and continues to increase rapidly, a relatively long propagation delay introduced by the buffer switch circuitry limits the ability of an emulator to provide trustworthy emulation of faster microprocessors.

One possible solution to satisfying the need for high-speed buffer switch circuitry has been to implement such circuitry in active transistor-transistor logic (TTL) or complementary metal oxide semiconductor (CMOS) technology. Such buffer circuits are attractive in that

they are readily available and each buffer switch stage produces additional signal drive. A disadvantage of suc buffer switches is that currently available microprocessors with typical cycle times of 20 nsec require the use of buffer switches having minimal propagation delay. Currently available TTL buffers and switches are major factors in limiting emulator performance. High-speed microprocessor designs require fast switching times in addition to low propagation delay times because of the limited decision-making time available to activate the switches implemented in the microprocessor.

Another possible solution has been the use of N channel field effect transistors (FETs) . It is known tha an N-channel FET can be switched to its electrically- conductive ("ON") state in anticipation of the arrival time of an applied data signal. A FET in its ON state provides a low impedance path with very little propagatio delay with the exception of that imparted by the electrical charging of a load capacitance through the ON-resistance of the FET. The ON-resistance of commercially available, closely packed arrays of FETs arranged to achieve component density is about 50 ohms. An N-channel FET driving a relatively large capacitive load of 100 pf through a 50 ohm ON-resistance produces a 5 nsec RC time constant that adds to the switching time required to enable the N-channel device. In addition, a high series resistance results in a signal voltage drop under load conditions. For example, a load driving 10 milliamperes through 50 ohms drops 0.5 volt. This voltage drop adversely impacts noise margins in digital systems.

A major disadvantage of an N-channel FET is that a gate terminal drive of 10 volts or greater is required to rapidly propagate a 5 volt peak-to-peak signal. This requires that a separate power supply be used to provide a

10 volt gate terminal voltage and that a separate transistor gate drive circuit be implemented for each N- channel FET in an array of FETs to achieve separate enabl control for each of them. A fairly complex gate drive circuit is used to minimize the amount of propagation delay through it. Typical switching times for an N- channel FET driven by such a separate gate drive circuit ranges between 5 and 10 nsec.

A third possible solution is the use of FET and gate drive components in die form and mounting several of them on ceramic substrates together with thin film resistors to produce an array of buffer switches with the desired component density. The implementation of this solution is relatively expensive and provides FETs with ON-resistances of about 50 ohms, which is undesirable for the reasons stated above.

Summary of the Invention An object of the present invention is, therefore, to provide an electronic signal switch with minimal propagation delay and low ON-resistance.

Another object of this invention is to provide such a switch with a drive circuit that does not add appreciable signal propagation delay and does not require additional power supply voltages. A further object is to provide a plurality of such switches arranged in a densely configured switch array.

The present invention is a CMOS switch circuit optimized for low ON-resistance and low propagation delay time. In a preferred embodiment, the present invention is implemented in a single integrated circuit as 8 channels of switches arranged in two groups of four switches, the groups being enabled by different gate drive circuits. The present invention is preferably used as a replacement for either active switch buffers or FET switch

buffers in high-speed digital isolation and switching applications. The advantages over active buffers are reduced power consumption and very low signal propagation delay once the switch is enabled, and the advantages over discrete FET buffers are higher channel density on an integrated circuit and simpler drive circuit requirements

Each group of four switches is enabled by a single-ended input and differential output drive circuit, which operates in response to an input signal switching between standard logic levels. Each drive circuit includes two similarly configured pairs of enhancement CMOS transistors. An input signal is applied to only one of the CMOS transistor pairs, which transistor pair produces an inverted replica of the input signal that is applied to the input of the other CMOS transistor pair. The outputs of the two CMOS transistor pairs produce a differential drive signal that enables each of the CMOS switches to which the drive signal is connected.

Each of the CMOS switches includes a pair of CMOS transistors with their drain terminals connected and their source terminals connected to form the input and output terminals of a bidirectional switch. Because the switch is bidirectional, its input and output terminals are interchangeable. The pair of CMOS transistors receives the differential drive signal at their gate terminals to enable the switch. The switch is biased so that, when it is enabled, a signal appearing at the input is conducted to the output.

The present invention is a CMOS switch whose switching speed and ON-resistance are optimized as a compromise over high channel-to-channel isolation, high electrically nonconducting ("OFF") state isolation, and linear performance across the switched signal voltage range. The optimization of these last three characteristics is a common analog switch design objective

for applications in which an analog waveform must be preserved. The invention in effect modifies a conventional analog switch circuit design to operate with digital signals to achieve isolation buffering for bidirectional signals and high density packing of multiple buffer switches operating under single enable control in a single package. Certain modifications to a conventional analog switch design that facilitate use of the present invention in high-speed digital switching applications provide rapid switching times (e.g.. 5 nsec) between ON and OFF states, a low ON-resistance of less than 25 ohms, high density configuration of multiple switches, and the ability to control the switches with standard logic-level signals. Additional objects and advantages of the present invention will be apparent from the following detailed description of a preferred embodiment thereof, which proceeds with reference to the accompanying drawings.

Brief Description of the Drawings Fig. 1 is a block diagram of a dual 4-channel

(octal) CMOS switch designed as a monolithic integrated circuit in accordance with the present invention.

Fig. 2 is an electrical circuit diagram of one of the two gate drive circuits depicted collectively in the block diagram of Fig. 1.

Fig. 3 is an electrical circuit diagram of one of eight CMOS switches depicted collectively in the block diagram of Fig. 1.

Detailed Description of Preferred Embodiment Fig. 1 is a simplified overall block diagram of an octal CMOS switch assembly 10 arranged as two similar subassemblies 12 and 14, each of which includes two groups 16 and 18 of four CMOS switches. In a preferred embodiment, switch assembly 10 is implemented as a monolithic integrated circuit. Groups 12 and 14 are

enabled by drive signals produced by respective single- ended input, differential output drive circuits 20 and 2

Drive circuits 20 and 22 receive at their respective input terminals 30 and 32 logic-level control signals that are used to enable the CMOS switches to whic the control signals are applied. Drive circuit 20 produces at its output terminals 34 and 36 a differential drive voltage signal that is applied to th respective noninverting enable and inverting enable input terminals of switch group 16, and drive circuit 22 produces at its output terminals 38 and 40 a differential drive voltage signal that is applied to the respective noninverting enable and inverting enable input terminals of switch group 18. The CMOS switches included in switch groups 16 and 18 have respective separate input terminals 46 and 48 to which a digital signal is applied. When they are enabled, switch groups 16 and 18 produce at their respective output terminals 50 and 52 signals that are replicas of the digital signals applied to their respective input terminals 46 and 48. When they are not enabled, switch groups 16 and 18 produce a high impedance OFF state at their respective output terminals 50 and 52. (For purposes of convenience only, the separate input and output terminals of the switches in each switch group are collectively identified by single reference numerals.) The implementation of the switches in CMOS provides complete logic-level switching with the logic-level enable capability. To achieve logic-level switching compatibility, positive and negative bias or reference voltages are connected to respective supply voltage terminals 54 and 56. In a preferred embodiment, supply voltage terminals 54 and 56 are connected to +5 volts and ground, respectively.

Fig. 2 is an electrical circuit diagram of driv circuit 20 to which the following description is directed but is equally applicable to drive circuit 22, which is o similar design to and operates in the same manner as driv circuit 20. With reference to Fig. 2, drive circuit 20 includes two similarly configured, matched pairs 62 and 6 of enhancement CMOS transistors. CMOS transistor pair 62 includes respective P-channel and N-channel transistors 6 and 68, whose gate terminals are connected to form input terminal 30 and whose drain terminals are connected to form output terminal 36. CMOS transistor pair 64 include respective P-channel and N-channel transistors 70 and 72, whose gate terminals are connected to output terminal 36 and whose drain terminals are connected to form output terminal 34.

The source and substrate terminals of P-channel transistors 66 and 70 are connected to +5 volt supply terminal 54, and the source and substrate terminals of N-channel transistors 68 and 72 are connected to ground terminal 56. Diodes 74 and 76 connected, respectively, between +5 volt supply terminal 54 and input terminal 30 and between ground terminal 56 and input terminal 30 to provide overvoltage protection for the gate terminals of CMOS transistor pair 62. CMOS transistor pair 62 receives at its input terminal 30 the logic-level control signal and develops at its output terminal 36 a signal that is delivered to two destinations. The signal appearing at output terminal 36 drives the inverting enable input terminals of switch group 16 and the gate terminals of CMOS transistor pair

64, which develops at its output terminal 34 a signal that drives the noninverting enable input terminals of switch group 36.

Each of the CMOS transistor pairs 62 and 64 operates as described below with reference to CMOS

transistor pair 62. Whenever the control signal applied to input terminal 30 is +5 volts, N-channel transistor 6 is biased to its ON state, thereby providing a conductiv path between the electrically connected drain terminals and ground, and P-channel transistor 66 is biased to its OFF state, thereby providing no conductive path between the drain and source terminals of transistor 66. Thus, zero volt signal appears at output terminal 36.

Whenever the control signal applied to input terminal 30 is zero volts, P-channel transistor 66 is biased to its ON state, thereby providing a conductive path between the electrically connected drain terminals and +5 volts, and N-channel transistor 68 is biased to it OFF state, thereby providing no conductive path between the drain and source terminals of transistor 68. Thus, a +5 volt signal appears at output terminal 36.

Each one of CMOS transistor pairs 62 and 64 functions as an inverter; therefore, configuring drive circuit 20 so that CMOS transistor pair 62 drives CMOS transistor pair 64 produces a differential output enable drive signal for switch group 16.

Skilled persons will appreciate that drive circuit 20 may be implemented as multiple series and/or parallel stages of the above-described electrical circuit to provide sufficient amplification to cause each of the switches in group 16 to rapidly transition between its operating states. The increased amplification would stem from a need to overcome the input capacitance of the larg CMOS switching transistors drive circuit 20 is intended to drive.

Fig. 3 is an electrical circuit diagram of one of the four CMOS switches included in group 16. The following description is directed to only one such CMOS switch but is equally applicable to any of the CMOS switches included in switch groups 16 and 18 because they

are of similar design and operate in the same manner. Although each CMOS switch has input and output terminals separate from those of the other switches of switch assembly 10, the reference numerals 46 and 50 are used only for purposes of convenience to indicate the respective input and output terminals of the CMOS switch described below.

With reference to Fig. 3, a CMOS switch includes a CMOS transistor pair 82 of respective P-channel and N-channel transistors 84 and 86, whose source terminals are connected to form digital signal input terminal 46 and whose drain terminals are connected to form output terminal 50. The substrate terminal of P-channel transistor 84 is connected to +5 volt supply terminal 54, and the substrate of N-channel transistor 86 is connected to ground terminal 56. The gate terminal of P-channel transistor 84 receives the inverting enable signal appearing on output terminal 36, and the gate terminal of N-channel transistor 86 receives the noninverting signal appearing on output terminal 34. Diodes 88 and 90 connected, respectively, between +5 volt supply terminal 54 and input terminal 46 and between ground terminal 56 and input terminal 46 provide overvoltage protection for the source terminals of CMOS transistor pair 82. Diodes 92 and 94 connected, respectively, between +5 volt supply terminal 54 and output terminal 50 and between ground terminal 56 and output terminal 50 provide overvoltage protection for the drain terminals of CMOS transistor pair 82. Diodes 92 and 94 are included because the digital signal input and output terminals of the bidirectional switch formed by CMOS transistor pair 82 are interchangeable.

CMOS transistor pair 82 receives at its input terminal 46 a digital signal, a buffered version of which appears at output terminal 50 depending on the switching

state of the noninverting and inverting enable signals appearing on the respective input terminals 34 and 36. Whenever a +5 volt signal appears on inverting enable input terminal 36 and a zero volt signal appears on noninverting enable input terminal 34, P-channel transistor 84 and N-channel transistor 86 are biased to the OFF state. Neither of the transistors in CMOS transistor pair 82 conducts electrical current under thes conditions, which represents the nonenabled switching state of the CMOS switch. Thus, a high impedance condition exists at output terminal 50 when CMOS transistor pair 82 is disabled, irrespective of the value of the digital signal applied to the source terminals of transistors 84 and 86 that form input terminal 46. Whenever a +5 volt signal appears on noninverting enable input terminal 34 and a zero volt signal appears on inverting enable input terminal 36, P-channel transistor 84 and N-channel transistor 86 are in a state in which they may be biased to the ON state by the digital signal applied to source terminals 84 and 86.

Both of the transistors in CMOS transistor pair 82 conduct electrical current in an amount that is a function of the digital signal voltage applied to input terminal 46 under these conditions, which represent the enabled switching state of the CMOS switch.

Whenever the digital signal applied to input terminal 46 reaches +5 volts, N-channel transistor 86 is biased to its OFF state and P-channel transistor 84 is biased to its ON state. This allows conduction of the digital signal from input terminal 46 through P-channel transistor 84 to its drain terminal, which is connected to output terminal 50. Whenever the digital signal applied to input terminal 46 reaches zero volts, P-channel transistor 84 is biased to its OFF state and N-channel transistor 86 is biased to its ON state. This allows

conduction of the digital signal from input terminal 46 through N-channel transistor 86 to its drain terminal, which is also connected to output terminal 50.

The voltage of the signal appearing on output terminal 50 follows the voltage of the signal applied to digital signal input terminal 46 when CMOS transistor pai 82 is in the enabled switching state. Skilled persons will appreciate that multiple CMOS transistor pairs 82 ma be connected in parallel to achieve the desired low ON- resistance characteristics.

Switch assembly 10 is intended preferably to be used in digital signal applications in which no propagation delay can be tolerated, and especially when large numbers of signals are present. Such applications include very fast digital buffers or multiplexers, devices requiring isolation buffering on bidirectional signals when the direction of drive is unobvious, and devices requiring single buffering but no requirement for drive amplification, especially in situations in which available power is limited.

The use of CMOS technology allows switch assembly 10 to switch over the complete logic-level voltage range using a logic-level control signal. This is in contrast to drive requirements characterizing discrete N-channel or P-channel FET switches, which require voltages outside the logic-level range to rapidly switch logic-level voltages. The relatively low ON-resistance of each of the CMOS switches of switch assembly 10 is provided by a relatively large CMOS transistor pair, which provides the signal path through the device. Because fast switching is also desired, internode capacitances within the switching elements are kept to a minimum by implementing switch assembly 10 in 1.25-micron geometry planar CMOS, with the switching FETs designed especially for this application.

It will be obvious to those having skill in the art that many changes may be made to the details of the above-described preferred embodiment of the present invention without departing from the underlying principle thereof. The scope of the present invention should, therefore, be determined only by the following claims.