Title:
HIGH SPEED RF DIVIDER
Document Type and Number:
WIPO Patent Application WO/2012/042044
Kind Code:
A3
Abstract:
High-speed RF differential, Quadrature, divide-by-2 clock divider designs are based on inverters and clocking circuits connected in a serial ring formation. In one embodiment, only NMOS transistors are used in the inverters, and only PMOS transistors are used in the clocking circuits. This structure uses only 12 transistors. The input can be coupled directly to a VCO output, and provides minimum loading, as each VCO output is connected to only two transistors. Another embodiment comprises clocked inverter stages connected in a serial ring configuration with inverters between stages. The RF clock (or VCO signal) is used at the outer side of the inverters for speed improvement. In both circuits, positive and negative clock inputs are connected alternately at each stage of the ring.
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Inventors:
HESEN LEONARDUS (NL)
MATEMAN PAUL (NL)
FRAMBACH JOHANNES PETRUS ANTONIUS (NL)
MATEMAN PAUL (NL)
FRAMBACH JOHANNES PETRUS ANTONIUS (NL)
Application Number:
PCT/EP2011/067188
Publication Date:
September 20, 2012
Filing Date:
September 30, 2011
Export Citation:
Assignee:
ST ERICSSON SA (CH)
HESEN LEONARDUS (NL)
MATEMAN PAUL (NL)
FRAMBACH JOHANNES PETRUS ANTONIUS (NL)
HESEN LEONARDUS (NL)
MATEMAN PAUL (NL)
FRAMBACH JOHANNES PETRUS ANTONIUS (NL)
International Classes:
H03K21/02; C07F7/08
Domestic Patent References:
| WO2004084412A1 | 2004-09-30 |
Foreign References:
| US20040198297A1 | 2004-10-07 | |||
| US20050127973A1 | 2005-06-16 | |||
| US20100039153A1 | 2010-02-18 | |||
| US4101790A | 1978-07-18 | |||
| FR2267666A1 | 1975-11-07 |
Attorney, Agent or Firm:
SOLLERHED, Mikael (P.O. Box 4188, Malmö, SE)
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