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Title:
HIGH SPEED RF DIVIDER
Document Type and Number:
WIPO Patent Application WO/2012/042044
Kind Code:
A8
Abstract:
High-speed RF differential, Quadrature, divide-by-2 clock divider designs are based on inverters and clocking circuits connected in a serial ring formation. In one embodiment, only NMOS transistors are used in the inverters, and only PMOS transistors are used in the clocking circuits. This structure uses only 12 transistors. The input can be coupled directly to a VCO output, and provides minimum loading, as each VCO output is connected to only two transistors. Another embodiment comprises clocked inverter stages connected in a serial ring configuration with inverters between stages. The RF clock (or VCO signal) is used at the outer side of the inverters for speed improvement. In both circuits, positive and negative clock inputs are connected alternately at each stage of the ring.

Inventors:
HESEN, Leonardus (Michelslaan 34, HC Hegelsom, NL-5963, NL)
MATEMAN, Paul (Heerbaan 60, ER Millingen aan de Rijn, NL-6566, NL)
FRAMBACH, Johannes Petrus Antonius (Meijhorst 16-24, KB Nijmegen, NL-6537, NL)
Application Number:
EP2011/067188
Publication Date:
May 02, 2013
Filing Date:
September 30, 2011
Export Citation:
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Assignee:
ST-ERICSSON SA (Chemin du Champ-des-Filles 39, Plan-les-Ouates, CH-1228, CH)
HESEN, Leonardus (Michelslaan 34, HC Hegelsom, NL-5963, NL)
MATEMAN, Paul (Heerbaan 60, ER Millingen aan de Rijn, NL-6566, NL)
FRAMBACH, Johannes Petrus Antonius (Meijhorst 16-24, KB Nijmegen, NL-6537, NL)
International Classes:
C07F7/08; H03K21/02
Attorney, Agent or Firm:
SOLLERHED, Mikael (Ström & Gulliksson AB, P.O. Box 4188, Malmö, S-203 13, SE)
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