Title:
HIGH-SPEED SERIAL DATA TRANSCEIVER SYSTEMS AND RELATED METHODS
Document Type and Number:
WIPO Patent Application WO2001084702
Kind Code:
A3
Abstract:
A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates. Each receiver includes a timing recovery system for tracking a phase and a frequency of the serial data signal associated with the receiver. The timing recovery system includes a phase interpolator responsive to phase control signals and a set of reference signals having different predetermined phases. The phase interpolator derives a sampling signal, having an interpolated phase, to sample the serial data signal. The timing recovery system in each receiver independently phase-aligns and frequency synchronizes the sampling signal to the serial data signal associated with the receiver. A receiver can include multiple paths for sampling a received, serial data signal in accordance with multiple time-staggered sampling signals, each having an interpolated phase.
Inventors:
BUCHWALD AARON
WAKAYAMA MYLES
LE MICHAEL
VAN ENGELEN JURGEN
JIANG XICHENG
WANG HUI
BAUMER HOWARD A
MADISETTI AVANINDRA
WAKAYAMA MYLES
LE MICHAEL
VAN ENGELEN JURGEN
JIANG XICHENG
WANG HUI
BAUMER HOWARD A
MADISETTI AVANINDRA
Application Number:
PCT/US2001/013637
Publication Date:
June 06, 2002
Filing Date:
April 30, 2001
Export Citation:
Assignee:
BROADCOM CORP (US)
International Classes:
H03L7/081; H03L7/091; H04L7/027; H04L7/033; H04L25/03; H03L7/07; (IPC1-7): H04L7/033; H03K5/13
Foreign References:
| EP0515074A2 | 1992-11-25 | |||
| US6002279A | 1999-12-14 | |||
| EP0909035A2 | 1999-04-14 | |||
| US5485490A | 1996-01-16 |
Other References:
SIDIROPOULOS S ET AL: "A SEMIDIGITAL DUAL DELAY-LOCKED LOOP", IEEE JOURNAL OF SOLID-STATE CIRCUITS, IEEE INC. NEW YORK, US, vol. 32, no. 11, 1 November 1997 (1997-11-01), pages 1683 - 1692, XP000752878, ISSN: 0018-9200
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