BACKGROUND

[0001] This disclosure relates generally to the field of voltage generating, and more particularly to a high voltage generation circuit and a high voltage generation method.

[0002] In many power generation systems, such as a downhole power generation system, it is required that a high direct current (DC) voltage is supplied to a load. Thus, such the power generation system usually needs a high voltage generation circuit to provide a desired voltage to the load.

[0003] A conventional high voltage generation circuit usually includes a voltage multiplier for multiplying to a higher voltage. The voltage multiplier includes a plurality of super capacitors which are connected in series. However, due to difference of the super capacitors, in the operation of the high voltage generation circuit, voltage unbalance of the super capacitors would be caused.

[0004] Therefore, in the view of the foregoing, a need how to achieve cell balancing for super capacitors in the condition of outputting a high voltage is becoming increasingly urgent.

BRIEF DESCRIPTION

[0005] In one aspect of embodiments of the present disclosure, a high voltage generation circuit is provided. The high voltage generation circuit comprises a battery for providing a first direct current voltage, a first inductance connected in series with the battery, a power switch and a voltage multiplier. The power switch is configured for converting the first direct current voltage to a pulse voltage. The voltage multiplier is configured for multiplying the pulse voltage to a second direct current voltage. The second direct current voltage is higher than the first direct current voltage. The voltage multiplier comprises super capacitors which are connected in series.

[0006] In another aspect of embodiments of the present disclosure, a high voltage generation method is provided. The high voltage generation method comprises: providing a first direct current voltage; converting the first direct current voltage, by a power switch, to a pulse voltage; and multiplying the pulse voltage, by a voltage multiplier comprising super capacitors connected in series, to a second direct current voltage, the second direct current voltage being higher than the first direct current voltage. DRAWINGS

[0007] These and other features, aspects, and advantages of the present disclosure will become better understood when the following detailed description is read with reference to the accompanying drawings in which like characters represent like parts throughout the drawings, wherein:

[0008] FIG. 1 is a schematic diagram of a high voltage generation circuit in accordance with a first embodiment of the present disclosure;

[0009] FIG. 2 is a schematic diagram of a high voltage generation circuit in accordance with a second embodiment of the present disclosure;

[0010] FIG. 3 is a schematic diagram of a high voltage generation circuit in accordance with a third embodiment of the present disclosure; and

[0011] FIG. 4 is a flow chart of an exemplary high voltage generation method in accordance with an embodiment of the present disclosure.

DETAILED DESCRIPTION

[0012] Embodiments of the present disclosure will be described hereinbelow with reference to the accompanying drawings. In the following description, well-known functions or constructions are not described in detail to avoid obscuring the disclosure in unnecessary detail.

[0013] Unless defined otherwise, technical and scientific terms used herein have the same meaning as is commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terms "first", "second", and the like, as used herein do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. Also, the terms "a" and "an" do not denote a limitation of quantity, but rather denote the presence of at least one of the referenced items. The term "or" is meant to be inclusive and mean either or all of the listed items. The use of "including," "comprising" or "having" and variations thereof herein are meant to encompass the items listed thereafter and equivalents thereof as well as additional items. The terms "connected" and "coupled" are not restricted to physical or mechanical connections or couplings, and can include electrical connections or couplings, whether direct or indirect. In addition, Terms indicating specific locations, such as "top", "bottom", "left", and "right", are descriptions with reference to specific accompanying drawings. Embodiments disclosed in the present disclosure may be placed in a manner different from that shown in the figures. Therefore, the location terms used herein should not be limited to locations described in specific embodiments.

[0014] First Embodiment of High Voltage Generation Circuit

[0015] FIG. 1 illustrates a schematic diagram of a high voltage generation circuit 100 in accordance with a first embodiment of the present disclosure. As shown in FIG. 1, the high voltage generation circuit 100 of the first embodiment may include a battery Vin, a first inductance Li, a power switch Si and a voltage multiplier M. The battery Vin can provide a first direct current (DC) voltage. The first inductance Li is connected in series with the battery Vin.

[0016] The power switch S i can convert the first DC voltage from the battery Vin to a pulse voltage. The power switch Si may be for example a transistor Si. A drain electrode d and a source electrode s of the transistor Si is coupled with the voltage multiplier M, and the source electrode s of the transistor Si is grounded. One terminal of the first inductance Li is connected with a positive terminal of the battery Vin and the other terminal of the first inductance Li is the drain electrode d of the transistor S i. The source electrode s of the transistor Si is connected to a negative terminal of the battery Vin.

[0017] The voltage multiplier M can multiply the pulse voltage to a second DC voltage. The second DC voltage is higher than the first DC voltage. Usually, the first DC voltage is a low voltage, and the second DC voltage is a high voltage. The voltage multiplier includes super capacitors which are connected in series.

[0018] The voltage multiplier M may include at least two multiplier stages Mi-M _n cascaded. Each of the at least two multiplier stages Mi-M _n has one of the super capacitors connected in series. Each of the at least two multiplier stages Mi-M _n has a first terminal 1, a second terminal 2 and a third terminal 3. For a first multiplier stage Mi, the first terminal 1 and the second terminal 2 of the first multiplier stage Mi are respectively connected with the drain electrode d and the source electrode s of the transistor Si. For a second multiplier stage M2 to a last multiplier stage M _n , the first terminal 1 and the second terminal 2 of one multiplier stage are respectively connected with the first terminal 1 and the third terminal 3 of a previous multiplier stage, and the third terminal 3 of the one multiplier stage is connected to the second terminal 2 of a next multiplier stage.

[0019] For example, the first terminal 1 and the second terminal 2 of the second multiplier stage M2 are respectively connected with the first terminal 1 and the third terminal 3 of the first multiplier stage Mi, and the third terminal 3 of the second multiplier stage M2 is connected to the second terminal 2 of the third multiplier stage M3. The first terminal 1 and the second terminal 2 of the third multiplier stage M3 are respectively connected with the first terminal 1 and the third terminal 3 of the second multiplier stage M ₂ , and the third terminal 3 of the third multiplier stage M3 is connected to the second terminal 2 of the fourth multiplier stage. The first terminal 1 and the second terminal 2 of the n ^th multiplier stage M _n are respectively connected with the first terminal 1 and the third terminal 3 of the (n-l) ^th multiplier stage.

[0020] Each of the at least two multiplier stages Mi-M _n may include a first capacitor, a second capacitor, a first diode and a second diode. For each multiplier stages Mi-M _n , the first capacitor and the first diode are connected in series between the first terminal 1 and the third terminal 3, the second diode is coupled between a connection point of the first capacitor and the first diode and the second terminal 2, and the second capacitor is coupled between the second terminal 2 and the third terminal 3.

[0021] For example, the first capacitor Ci and the first diode D2 of the first multiplier stage Mi are connected in series between the first terminal 1 and the third terminal 3 of the first multiplier stage Mi, the second diode Di of the first multiplier stage Mi is coupled between a connection point of the first capacitor Ci and the first diode D2 and the second terminal 2 of the first multiplier stage Mi, and the second capacitor C _s i of the first multiplier stage Mi is coupled between the second terminal 2 and the third terminal 3 of the first multiplier stage Mi. The first capacitor C2 and the first diode D4 of the second multiplier stage M2 are connected in series between the first terminal 1 and the third terminal

3 of the second multiplier stage M ₂ , the second diode D3 of the second multiplier stage M2 is coupled between a connection point of the first capacitor C2 and the first diode D4 and the second terminal 2 of the second multiplier stage M ₂ , and the second capacitor C _S 2 of the second multiplier stage M2 is coupled between the second terminal 2 and the third terminal 3 of the second multiplier stage M ₂ . The first capacitor C3 and the first diode D6 of the third multiplier stage M3 are connected in series between the first terminal 1 and the third terminal 3 of the third multiplier stage M3, the second diode D5 of the third multiplier stage M3 is coupled between a connection point of the first capacitor C3 and the first diode D6 and the second terminal 2 of the third multiplier stage M3, and the second capacitor C _S 3 of the third multiplier stage M3 is coupled between the second terminal 2 and the third terminal 3 of the third multiplier stage M3. The first capacitor Cn and the first diode Om of the n ^th multiplier stage M _n are connected in series between the first terminal 1 and the third terminal 3 of the η ^Λ multiplier stage Mn, the second diode D _2n -i of the n ^th multiplier stage M _n is coupled between a connection point of the first capacitor Cn and the first diode D2n and the second terminal 2 of the n ^th multiplier stage M _n , and the second capacitor C _S n of the n ^th multiplier stage M _n is coupled between the second terminal 2 and the third terminal 3 of the n ^th multiplier stage Mn. The second capacitor Csi-Csn of each multiplier stage Mi-Mn is the super capacitor.

[0022] The high voltage generation circuit 100 of the present disclosure use a single switch based voltage multiplier to achieve a high voltage output and achieve cell balancing for the super capacitor Csi-Csn of each multiplier stage Mi-M _n . The high voltage generation circuit 100 of the present disclosure can have long life time, low power consumption, compact size and low cost.

[0023] Second Embodiment of High Voltage Generation Circuit

[0024] FIG. 2 illustrates a schematic diagram of a high voltage generation circuit 200 in accordance with a second embodiment of the present disclosure. As shown in FIG. 2, different from the first embodiment, in the basis of the high voltage generation circuit 100 of FIG. 1, the high voltage generation circuit 200 of the second embodiment may further include a resonant circuit 40. The resonant circuit 40 is coupled between the power switch Si and the voltage multiplier M, and can convert the pulse voltage to a resonant voltage. Under this circumstance, the voltage multiplier M can multiply the resonant voltage to the second DC voltage.

[0025] The resonant circuit 40 includes the first inductance Li, a third capacitor Cpi, a fourth capacitor Cs and a second inductance Ls. The third capacitor CPI is connected in parallel with the power switch S ι. The fourth capacitor Cs and the second inductance Ls are connected in series between the third capacitor CPI and the voltage multiplier M.

[0026] Similarly, the high voltage generation circuit 200 of the present disclosure can achieve a high voltage output and achieve cell balancing for the super capacitor Csi-Csn of each multiplier stage Mi-Mn. The high voltage generation circuit 200 of the present disclosure can have long life time, low power consumption, compact size and low cost.

[0027] Third Embodiment of High Voltage Generation Circuit

[0028] FIG. 3 illustrates a schematic diagram of a high voltage generation circuit 300 in accordance with a third embodiment of the present disclosure. As shown in FIG. 3, different from the second embodiment, in the basis of the high voltage generation circuit 200 of FIG. 2, the high voltage generation circuit 300 of the third embodiment may further include an isolated transformer T. The isolated transformer T is coupled between the resonant circuit 40 and the voltage multiplier M. The transformer T has a primary winding Wi coupled with the resonant circuit 40 and a secondary winding W ^~ 2 coupled with the voltage multiplier M.

[0029] The high voltage generation circuit 300 may further include a fifth capacitor CP2. The fifth capacitor CP2 is coupled in parallel between the secondary winding W2 of the transformer T and the voltage multiplier M.

[0030] Similarly, the high voltage generation circuit 300 of the present disclosure can achieve a high voltage output and achieve cell balancing for the super capacitor C _s i-C _S n of each multiplier stage Mi-Mn. The high voltage generation circuit 300 of the present disclosure can have long life time, low power consumption, compact size and low cost.

[0031] High Voltage Generation Method

[0032] FIG. 4 illustrates a flow chart of an exemplary high voltage generation method in accordance with an embodiment of the present disclosure. The high voltage generation method in accordance with an embodiment of the present disclosure may include the steps as follows.

[0033] As shown in FIG. 4, in block B 1 , a first direct current voltage may be provided, for example by a battery Vin.

[0034] In block B2, the first direct current voltage may be converted to a pulse voltage by a power switch S i, for example a transistor.

[0035] In block B3, the pulse voltage may be multiplied to a second DC voltage by a voltage multiplier M comprising super capacitors connected in series. The second DC voltage is higher than the first DC voltage. Thus, a high voltage output can be achieved.

[0036] In an optional embodiment, the high voltage generation method of the present disclosure may further include a block B4 after block B2 and before block B3.

[0037] In block B4, the pulse voltage may be converted to a resonant voltage, for example by a resonant circuit 40 (as shown in FIG. 2), and then the process goes to block B3. In the embodiment including block B4, in block B3, the resonant voltage may be multiplied to the second DC voltage.

[0038] In another optional embodiment, the high voltage generation method of the present disclosure may further include a block B5 after block B4 and before block B3. [0039] In block B5, the resonant voltage may be converted to a third AC voltage, for example by an isolated transformer T (as shown in FIG. 3), and then the process goes to block B3. In the embodiment including block B4 and block B5, in block B3, the third AC voltage may be multiplied to the second DC voltage. The value of the first DC voltage is less than the value of the third AC voltage and the value of the third AC voltage is less than the value of the second DC voltage.

[0040] The high voltage generation method of the present disclosure can achieve a high voltage output and have low power consumption.

[0041] While steps of the high voltage generation method in accordance with embodiments of the present disclosure are illustrated as functional blocks, the order of the blocks and the separation of the steps among the various blocks shown in FIG. 4 are not intended to be limiting. For example, the blocks may be performed in a different order and a step associated with one block may be combined with one or more other blocks or may be sub-divided into a number of blocks.

[0042] While the disclosure has been illustrated and described in typical embodiments, it is not intended to be limited to the details shown, since various modifications and substitutions can be made without departing in any way from the spirit of the present disclosure. As such, further modifications and equivalents of the disclosure herein disclosed may occur to persons skilled in the art using no more than routine experimentation, and all such modifications and equivalents are believed to be within the spirit and scope of the disclosure as defined by the following claims.