FIELD OF THE INVENTION

[0001] The present invention relates to semiconductor devices, and more particularly, to a host substrate for nitride-based light emitting devices.

BACKGROUND OF THE INVENTION

[0002] Light emitting diodes (LEDs) is currently one of the most innovative and fastest growing technologies in the semiconductor industry. While LEDs have been in use for decades as indicators and for signaling purposes, technology developments and improvements have allowed for a broader use of LED in illumination applications. [0003] Semiconductors that contain nitrogen (N) as the Group V element have proven to be useful for short-wavelength light emitting devices. Among these, extensive research has been conducted on gallium-nitride based semiconductors for use as light emitting diodes, such as In _x GaI - _X N and Al _x Ga _y ln _z N, and such LED have already been put to practical use.

[0004] Generally, GaN-based LED are grown on a sapphire substrate. The GaN semiconductor layers are grown on a sapphire substrate. But sapphire is not a good thermal or electrical conductor, so a host substrate is then attached to the GaN semiconductor layers and the sapphire is removed. The host substrate must satisfy many requirements, such providing sufficient mechanical support, providing good thermal and electrical conductivity, and CTE (coefficient of thermal expansion) matching. CTE mismatch can result in large amounts of stress, which results in cracks in the GaN layers and reliability problems.

[0005] Presently known materials for substrate substitution have a number of limitations. For example, a pure metal such as Cu, while providing thermal and electrical conductivity, has a large CTE mismatch, is too soft and not easy to use in a device fabrication process, and difficult to be diced with a cutting street width less than 100 urn by either laser or dicing saws. SU8 can be used to separate the copper substrate before plating, but this process increases costs and process difficulty. Moreover, can be hard to incorporate such devices into integrated circuits based on silicon. For metal alloys, such as copper tungsten (CuW), while providing better CTE matching, a high volume of tungsten is required, which can degrade the performance of copper. For a pure semiconductor material, such as silicon, it is cheap and easy to integrate devices into circuits. However, a pure semiconductor material provides much less thermal and electrical conductivity than copper and limits the device performance when scaling up the size of the LEDs.

[0006] Accordingly, there is a need for an LED substrate that addresses these and other shortcomings of known substrate materials.

SUMMARY OF THE INVENTION

[0007] According to one embodiment of the present invention, a method of making a host substrate for nitride based thin-film semiconductor devices is disclosed. The method includes the steps of providing a semiconductor layer; etching a pattern of holes in the semiconductor layer; plating the semiconductor layer with metal to fill the holes formed in the semiconductor layer; bonding the semiconductor layer to a gallium nitride (GaN) layer, the GaN layer attached to a sapphire substrate; and removing the sapphire substrate.

[0008] According to another embodiment of the present invention, a method of making a host substrate for nitride based thin-film semiconductor devices is disclosed. The method includes the steps of providing a silicon layer; etching a pattern of blind holes in a side of the silicon layer; bonding the silicon layer to a gallium nitride (GaN) layer, the GaN layer attached to a sapphire substrate, wherein the side of the silicon layer having the pattern of holes is bonded to the GaN layer; thinning the silicon layer to expose the pattern of holes in the silicon layer; plating the silicon layer with copper to fill the holes formed in the silicon layer; and removing the sapphire substrate. [0009] According to another embodiment of the present invention, a nitride based semiconductor structure having a host substrate is disclosed. The nitride-based semiconductor includes a sapphire substrate; one or more semiconductor layers formed on the substrate, wherein one of the one or more semiconductor layers includes a plurality of metal sections, wherein the silicon layer defines a plurality of holes patterned in the silicon layer, and the plurality of metal sections include metal filled in the plurality of holes.

[0010] According to another embodiment of the present invention, a nitride based semiconductor structure having a host substrate is disclosed. The nitride-based semiconductor includes a sapphire substrate; one or more gallium nitride (GaN) layers formed on the sapphire substrate; a metal layer plated to the one or more GaN layers; and a semiconductor layer bonded to the metal layer.

[0011] According to another embodiment of the present invention, a nitride based semiconductor structure having a host substrate is disclosed. The nitride-based semiconductor includes a sapphire substrate; one or more gallium nitride (GaN) layers formed on the sapphire substrate; a metal layer plated to the one or more GaN layers, wherein the metal layer includes a combination of two different metals. [0012] Still other embodiments of the present invention will become readily apparent to those skilled in the art from the following detailed description, wherein embodiments of the invention are described by way of illustration. As will be realized, the invention is capable of other and different embodiments and its several details are capable of modifications in various respects, all without departing from the spirit and the scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] FIG. 1 is a partial cross sectional view of a semiconductor structure, in accordance with an embodiment of the present invention.

[0014] FIG. 2 is a partial cross sectional view of a semiconductor structure, in accordance with an embodiment of the present invention.

[0015] FIG. 3 is a partial cross sectional view of a semiconductor structure, in accordance with an embodiment of the present invention.

[0016] FIG. 4 is a partial cross sectional view of a semiconductor structure, in accordance with an embodiment of the present invention.

[0017] FIG. 5 is a partial cross sectional view of a semiconductor structure, in accordance with an embodiment of the present invention.

[0018] FIG. 6 is a partial cross sectional view of a semiconductor structure, in accordance with an embodiment of the present invention.

[0019] FIG. 7 is a partial cross sectional view of a semiconductor structure, in accordance with an embodiment of the present invention.

[0020] FIG. 8 is a partial cross sectional view of a semiconductor structure, in accordance with an embodiment of the present invention.

[0021] FIG. 9 is a partial cross sectional view of a semiconductor structure, in accordance with an embodiment of the present invention.

[0022] FIG. 10 is a partial cross sectional view of a semiconductor structure, in accordance with an embodiment of the present invention.

[0023] FIG. 11 is a partial cross sectional view of a semiconductor structure, in accordance with an embodiment of the present invention.

[0024] FIG. 12 is a partial cross sectional view of a semiconductor structure, in accordance with an embodiment of the present invention. [0025] FIG. 13 is a plan view of the semiconductor structure shown in FIGS. 6 and 11 , in accordance with an embodiment of the present invention.

[0026] FIG. 14 is a partial cross sectional view of a semiconductor structure, in accordance with an embodiment of the present invention.

[0027] FIG. 15 is a partial cross sectional view of the semiconductor structure shown in FIG. 14, with the sapphire substrate removed, in accordance with an embodiment of the present invention.

[0028] FIG. 16 is a partial cross sectional view of a semiconductor structure, in accordance with an embodiment of the present invention.

[0029] FIG. 17 is a partial cross sectional view of the semiconductor structure shown in FIG. 16, with the sapphire substrate removed, in accordance with an embodiment of the present invention.

DETAILED DESCRIPTION

[0030] In the following description, reference is made to the accompanying drawings where, by way of illustration, specific embodiments of the invention are shown. It is to be understood that other embodiments may be used as structural and other changes may be made without departing from the scope of the present invention. Also, the various embodiments and aspects from each of the various embodiments may be used in any suitable combinations. Accordingly, the drawings and detailed description are to be regarded as illustrative in nature and not as restrictive.

[0031] Generally, embodiments of the present invention are directed to stacked host substrate for use in LED fabrication processes. The host substrate combines both semiconductor materials and metals as a new conductive substrate for nitride based, thin-film semiconductor devices. Embodiments of the present invention include semiconductor materials for the cutting street areas, while the metals are inserted for mechanical support as well as a thermal and electrical conductor in the active regions. Several methods are described to create such a substrate structure according to embodiments of the present invention.

[0032] One example method includes etching a pattern of holes in a semiconductor layer, such as silicon layer, plating the silicon layer with a metal, such as copper, to fill the holes etched in the silicon layer; bonding the silicon layer to a gallium nitride (GaN) layer, the GaN layer attached to a sapphire substrate; and removing the sapphire substrate. Another example method includes etching a pattern of blind holes in a semiconductor, such as silicon, bonding the semiconductor to a GaN layer, the GaN layer attached to a sapphire substrate; thinning down the silicon layer to expose the patterned holes; plating the metal such as copper inside the silicon; and removing the sapphire substrate.

[0033] According to embodiments of the present invention, the host substrate includes a combination of material combined in way that produces an efficient, reliable light emitting device. Embodiments of the host substrate provide better mechanical support than pure copper, maintain the a high level of thermal and electrical conductivity, reduce stress caused by CTE mismatch problems, allows for easy cutting, and may be integrated with circuits. One embodiment of the present invention includes a host substrate comprising of silicon and copper.

[0034] FIGS. 1 to 6 are cross sectional views illustrating the process flow of one example method of fabricating the host substrate and attaching it to the nitride layers. FIGS. 7 to 12 are cross sectional views illustrating the process flow of another example method of fabricating the host substrate and attaching it to the nitride layers. FIG. 13 is a plan view of the semiconductor structure shown in both FIG. 6 and FIG. 11. [0035] Referring now to the figures, FIG. 1 is a partial cross sectional view of a layer of silicon (Si) 100. As shown in FIG. 2, the silicon is then patterned and a plurality of holes 102 are etched into the silicon 100 to a predetermined depth. Any suitable depth may also be used. Any suitable pattern and size and shape of holes may be etched into the silicon. One example depth is greater than 5 urn. Another example depth is approximately 100 urn. Referring to FIG. 3, copper (Cu) plating 300 is then used to fill and cover the holes 102. Referring to FIG. 4, a polishing or mechanical planarization is used to remove the excess copper 300. Accordingly, a host substrate comprising silicon 100 and copper 300 is provided.

[0036] Referring to FIG. 5, the host substrate is bonded to one or more GaN layers 500 of a semiconductor structure. The one or more GaN layers 500 are formed on a sapphire substrate 502. Referring to FIG. 6, the silicon 100 is polished to expose the copper 300 in the host substrate. In the resulting semiconductor structure shown in FIG. 6, the copper 300 and silicon 100 have a parallel connection to a p-GaN layer of the one or more GaN layers 500. Because Cu has better conductivity, Cu and Si have a parallel connection to the p-GaN, the heat and the current will mostly pass through the copper 300, therefore the host substrate may provide similar heat dissipation and electrical conductivity as a copper substrate.

[0037] Referring now to FIGS. 7 to 11 , a semiconductor structure fabrication process using a host substrate is shown, according to a second embodiment of the present invention. FIG. 7 is a partial cross sectional view of a layer of silicon (Si) 800. Referring now to FIG. 8, the silicon is then patterned and a plurality of holes 802 are etched into the silicon 800 to a predetermined depth. Any suitable pattern and size and shape of holes may be etched into the silicon. One example depth is approximately 100 um. Referring to FIG. 9, the silicon layer 800 is bonded to one or more GaN layers 1000 of a semiconductor structure. The one or more GaN layers 1000 are formed on a sapphire substrate 1002. Referring to FIG. 10, the silicon 100 is polished to expose the holes that were etched into the silicon 800. Referring to FIG. 11 , copper (Cu) 1200 plating is then used to fill and cover the holes 802. If necessary, a polishing or mechanical planarization process may be used to remove any excess copper 1200. Accordingly, a host substrate 1204 comprising silicon 100 and copper

300 is provided.

[0038] In the resulting semiconductor structure shown in FIG. 11 , similar to the first embodiment of the fabrication process illustrated in FIGS. 1 to 6, the copper 1200 and silicon 800 have a parallel connection to a p-GaN layer of the one or more GaN layers

1000, and therefore, the semiconductor structure provides similar advantages.

[0039] Referring now to FIG. 12, the sapphire substrate 1002 of the semiconductor structure shown in FIG. 11 has been removed.

[0040] Referring now to FIG. 13, a plan view of the semiconductor structure 1300 shown in FIGS. 6 and 11 is shown, in accordance with an embodiment of the present invention. Similar to the semiconductor shown in FIG. 7, the semiconductor structure shows the silicon 800 and a pattern of copper 1200 filled into the silicon 800 layer.

Dashed lines 1302 illustrate dicing streets in the semiconductor structure 1300. The dicing streets a located in the silicon portion of the semiconductor structure. Therefore, cutting of the semiconductor structure 700, 1300 can be made by cutting through the silicon 100, 800 portion of the semiconductor structure, and other circuit modules can be fabricated in the silicon areas and integrated with LEDs as a driver or to perform other functions.

[0041] One advantage of the second embodiment of the fabrication process, illustrated in FIGS. 7 to 11 , and in other embodiment, is that the host substrate may be more easily bonded to the GaN layer because it is easier to bond one flat material to another flat material. However, both the first and second embodiment of the fabrication processes may be used, and both produce a resulting host substrate with improvements over the prior art.

[0042] FIG. 14 is a partial cross sectional view of a semiconductor structure 1400, in accordance with an embodiment of the present invention. The semiconductor structure 1400 includes a sapphire substrate 1402, one or more GaN layers 1404, and a host substrate 1406 bonded to the one or more GaN layers 1404. The host substrate 1406 includes a combination of alternating copper (Cu) 1408 and nickel (Ni) 1410. The semiconductor structure shown in FIG. 14 is fabricated similar to either the process illustrated and described with reference to FIGS. 1 to 6 or the process illustrated and described with reference to FIGS. 8 to 12. However, in either process, a first lithography process is used to selectively plate the first metal, either copper or nickel, and then a second lithography process is used to selectively plate the second metal into the voids left by the first lithograph process, either copper or nickel, depending on which was used in the first lithograph process.

[0043] The host substrate 1406 relieves stress by separating the copper into different areas and inter-cross plating the copper with a second metal having lower thermal expansion. Therefore, there is less warping and expansion when compared to the use of a copper substrate. One example of inter-cross plating includes alternating strips of the copper and the second metal. Another example of inter-cross plating includes alternating sections of the copper and the second metal, the sections being any shape and size adjacent to each other on the surface of the one or more GaN layers 1404. Embodiments of the present invention may include the host substrate 1406 having two or more different types of metal.

[0044] FIG. 15 is a partial cross sectional view of the semiconductor structure shown in FIG. 14, with the sapphire substrate removed, in accordance with an embodiment of the present invention.

[0045] FIG. 16 is a partial cross sectional view of a semiconductor structure, in accordance with an embodiment of the present invention. The semiconductor structure 1600 includes a sapphire substrate 1602, one or more GaN layers 1604 formed on the sapphire substrate 1602, a layer of copper 1606 plated to the one or more GaN layers 1604, a bonding metal 1607, and a layer of silicon 1608 bonded to the layer of copper 1606 with any suitable bonding metals 1610. A host substrate, therefore, is a stacked substrate comprising a metal stacked with a semiconductor. The illustrated embodiment includes the layer of copper 1606 and the layer of silicon 1608, and any necessary bonding metals 1610.

[0046] The host substrate and the semiconductor structure 1600 may be formed using any suitable lithography and bonding methods. According to one example process, less than 100um of copper 1606 is electroplated on to the one or more GaN layer 1604. The silicon layer 1608 is bonded to copper layer 1606 by thermo compression, solder bonding, or eutectic bonding at a relatively high temperature, such as, for example, a temperature greater than or approximately equal to 200 degrees centigrade.

[0047] Embodiments of the of the host substrate shown in FIGS. 16 and 17 result in a semiconductor device with less warping and more convenient device fabrication. The host substrate also provides improved mechanical support and greater thermal and electrical conductivity when compared to silicon.

[0048] FIG. 17 is a partial cross sectional view of the semiconductor structure shown in FIG. 16, with the sapphire substrate removed, in accordance with an embodiment of the present invention.

[0049] Embodiments of the present invention provide a number of advantages over the prior art. According to one embodiment, the host substrate can be used to reduce the amount of stress when compared to a copper substrate because it's applied to a smaller area. The thermal and electrical conductivity of the host substrate according to embodiments of the present invention are comparable to copper when the by optimizing the designs. Additionally, integration with circuits is possible with embodiments of the present invention, because at least some areas of the host substrate are reserved for silicon, and other devices can be built upon the silicon. [0050] While the invention has been particularly shown and described with reference to the illustrated embodiments, those skilled in the art will understand that changes in form and detail may be made without departing from the spirit and scope of the invention. For example, certain etching patterns are illustrated and described, any other suitable etching patterns may be used and those shown are provided for the purpose of illustration. Similarly, while certain materials are specified, other materials and metals having similar properties and providing a similar result may also be used. For example, some suitable materials for use as the semiconductor layer may include Si, Ge, GaAs, IN-V nitride, InP and ZnO. The embodiments of the present invention should therefore not be limited to these specified materials. Also, while a certain depth of holes has been indicated for the copper plating, other suitable depts. May be considered and used so as to avoid or minimize interconnection issues. [0051] Accordingly, the above description is intended to provide example embodiments of the present invention, and the scope of the present invention is not to be limited by the specific examples provided.