Background of the invention

The present invention relates to compression of digital image data and the recreation of an image from the recorded digital data. More specifically, the present 5 invention relates to parallel implementation of a Huffman decoder for data string decompression during recreation of the image.

Summary of the Prior Art

The practice of data compression and decompression is

10 generally known in the art. Similarly, the use of Huffman encoding/decoding schemes is also well known in the art. In the case of photographic images, once an eight by eight pixel block has been allocated, and a discrete cosine transformation (DCT) preformed thereon, the resultant DCT

15 values are processed. The processing of these DCT values

(or frequencies, as described in the Detailed Description) includes scaling and entering them into a Huffman table where Huffman coding operations are performed. The result of Huffman encoding is reduced length code for the proces-

20 sed data. .

During a normal prior art compression cycle, a Huffman coder is used to translate an eight bit word, indicative of a certain DCT scaled frequency into a variable length code.

The more commonly occurring eight bit word values are

25 assigned smaller variable length codes. A ROM is used to

effect the translation. The output of the ROM is a code

(representative of an eight bit word) , plus a number which indicates how many bits are in the particular code. Thus, a data string is formed of codes followed by the data for that particular code. The process for generating this data string is generally known in the art. One clock pulse is required per data word created.

A problem arises, however, in the decoding phase when it is necessary to extract the original eight bit data value from the coded data. Sequential logic which looks at one bit at a time has been utilized. In sequential logic implementations, a state machine or decision "tree" is established and used to decode compress data words. A data string enters the tree, one bit per clock pulse, until the data bits in the tree find a match down the particular branches and leaves of the decision tree. The problem with this solution is twofold. One, it is slow (since the logic works one bit at a time) . This problem is compounded because state machines can be very complex, especially when the coded data can be up to 16 or 20 bits.

A second problem is that every change in the content of the Huffman table for the state machine may cause a significant change in the implementation of the state machine. That is because the decision tree will not be the same and a whole new decision tree will have to be gener¬ ated, which is very complex.

SUMMARY OF THE INVENTION

Accordingly, it is the object of the present invention to provide a decompression apparatus with a parallel implementation of a Huffman decoder which will operate faster than sequential logic.

It is another object of the present invention to provide a decompression apparatus with an implementation of a Huffman decoder that is simpler to implement.

It is still another object of the present invention to provide a decompression apparatus wherein any change in a

Huffman table content causes only one mask change which can be accomplished on a computer and does not affect other logic or die size.

The attainment of these and related objects may be achieved through use of the novel Huffman data string decompression apparatus and method herein disclosed. A Huffman data string decompression apparatus and method in accordance with this invention has an apparatus for decoding a compressed data bit string, having a data string positioner for designating a predefined portion a data bit string to be decompressed and a programmable logic array having a Huffman table programmed therein for si ultane- ously receiving the portion of the data bit string and for matching at least a particular unique sequence of bits in the portion to a sequence within the table. Also included are an output device responsive to the programmable logic array for producing a decompressed code value for the matched unique sequence on bits, and a mechanism for updating the data bit string positioner to designated a next portion of the bit string.

The attainment of the foregoing and related objects, advantages and features of the invention should be more readily apparent to those skilled in the art, after review of the following more detailed description of the inven¬ tion, taken together with the drawings, in which:

BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 is a diagram of general data compression techniques.

Figure 2 is a block diagram of the parallel Huffman decoder of the preferred embodiment.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

Referring to Figure 1, an exemplary diagram of the process for encoding photographic data is shown. An image to be digitally reproduced is broken down into a plurality of eight by eight pixel blocks 11a. Each of these frames

11a undergoes a digital coefficient transformation (DCT) , plus scaling, to produce a similar sized matrix that contains scaled DCT frequencies lib. Both the procedure for conducting such a transformation and the reasons why such a transformation is necessary are well known in the art. The DCT transforms the digital picture data contained in the pixels into a collection of the frequencies lib. For a particular eight by eight collection of scaled frequencies lib, a value is assigned to each frequency. A prior analysis is done of which frequency values appear most frequently and those frequencies are assigned the smallest of the variable length codes. Huffman table is then generated based on this prior analysis.

An example of the encoding process is as follows. For each scaled frequency in frame - lib, a 16 bit value is assigned. Picking an arbitrary scaled frequency 12, in the middle of the central portion of the image 10, the 16 bit assigned value is 0000 0000 1011 1101. An eight bit word 14 is created to encode information for scaled frequency 12. In a frame lib, most of the 16 bit values will be all zeros. Of the ones that are not, a substantial portion of those will have leading zeros. Therefore, when a frequency having a non-zero 16 bit value is encountered, the first four bits 14a of its eight bit word 14 contain the number of preceding all zero 16 bits words. For the eight bit word 14 of frequency 12, the number of preceding immediate¬ ly all zero 16 bit words is seven. The second four bits 14b of the eight bit word 14 indicate the number of bits in the 16 bit word that actually contain data. In this instance, that number is eight.

Another example of this encoding scheme is illustrated with reference to eight bit word 16. We will assume that

another scaled frequency value has a 16 bit word value of

0000 0000 0000 0011. If this value is preceded by eleven pixels of zero value, the first four bits 16a contain the binary representation for eleven. Since there are only two bits of actual data, the second four bits 16b of eight bit word 16 contain the binary representation for two.

All eight bit encoded words 14 and 16 and associated data bits are sent to a Huffman table 18. The Huffman table 18 produces an output for each word 14 and 16. The output consists of two parts. The first part is a variable length code indicative of image data. The second part is a number which tells how long the variable length code is. A plurality of codes and associated data are output from the Huffman table 18 until a data bit string of picture information is created. A special code for end of block (EOB) is attached at the end of each block. This data string represents the encoded digital image and can be stored relatively efficiently in memory.

When it is desired to recreate the encoded image, the data string is retrieved from memory and the data decoded.

As discussed previously, prior art attempts to decode the data string have been quite time consuming, processing the encoded data string one bit at a time in a state machine. The present invention addresses this shortcoming in data string processing by processing data string bits in parallel, as opposed to serial.

Referring to Figure 2, a block diagram of the prefer¬ red embodiment is shown. In the preferred embodiment the decoder 40 reads in 20 bits, in parallel, from the data string. The number 20 is selected because the coder utilized in the encoding stage (Figure 1) produces a largest code length of that size. This number, 20, however, is arbitrary and can be changed to accommodate other length codes. The use of a 16 bit word length may be preferable in some instances because it is a common length word size.

The 20 bits are shifted from a shift register 42 to a programmable logic array (PLA) 44. The PLA 44 has 21 inputs, 20 for data and 1 for enabling. Input line 43 carries a signal which enables the PLA 44 when it is to be used. The PLA 44 is turned off otherwise to conserve power. The remaining 20 inputs are shifted over, one 20 bit. shift per clock pulse, into a first section 46 of the PLA 44. This first section 46 contains the minterms. As will be described in more detail below, the minterms are connected to an associated output code in a second, or output, section 48 of the PLA 44. The output of the second section 48 is 13 bits wide. Eight of these bits represent output code, the other five indicate the length of the input compressed code in the initially shifted 20 bits.

The data string to be decoded, or at least a portion thereof, is extracted from memory and placed in a buffer 50. The data string is moved from the buffer 50 to shifter register 42 where 20 data bits are shifted to the first section 46 of the PLA 44. The first section 46 contains 256 minterms (these are represented as vertical lines) . The contents of the minterms are predetermined values that are unique and will match to a particular input code sequence in the 20 bits shifted in. The substantive value of the minterms is created from the same Huffman table 18 used in encoding the data. Creating a Huffman decoding array is well known in the art.

Although 20 bits are shifted into the PLA 44, it is rare that all 20 bits are utilized. For example, the first seven bits may find a match in the first minterm (repre- sented as the first column from the left in the PLA 44) . In that instance, 13 of the initially shifted 20 bits are not used. Those 13 bits, after removal of data bits for the matched seven bit code, will now become the first 13 bits on the next 20 bit word to be shifted into the PLA 44.

For every minterm there is an eight bit decompressed code associated therewith. The special eight bit code is the decompressed versions of the compressed eight bit words (14 and 16 of Figure 1, for example) . These eight bit codes are resident in the second section 48 of the PLA 44. When a match is made to a particular minterm, the minterm line is activated propagating a signal to the second section 48 that causes the associated eight bit code to move to the output 49 of the PLA 44. The right most four bits of the eight bit output code is used to remove the actual data from the data string. The eight bit output code is accompanied by a five bit preprogrammed code that indicates the number of data bits, of the 20, that were utilized in matching the minterm. The eight bit code is output for final decompression, while the five bit indi¬ cator is used to update the data string pointer in the buffer 50 and shift register 42.

The five bit value indicative of the number of bits used to match a minterm are transmitted from the second section 48 to an adder 52. The ^" five bit number is then sent through buffer 50 to shift register 42. In order to update the shift register 42, the amount of bits designated in the five bit value is subtracted from the data string. The next 20 bits are then shifted to the PLA 44 and the operation repeats itself until the whole data string has been processed.

In the above case of the seven bits of compressed data matched to the first minterm, the five bit value would indicate a seven bit length that would then be propagated to the buffer 50 and shifter 42 to update the data string. In another example, the first ten bits of the data string may match to the second minterm (column 2) . The third minterm (column 3) indicates when the first bit in the data string creates a match. In the case of the second minterm, 10 bits are removed from the input data string. For the third minterm, one bit is removed from the input data string before the next 20 bit shift occurs. On an addi-

tional note, the reason there are 256 minterms is because the output code has eight bits. Since the minterms are unique and each one indicates a separate eight bit word, there are 256 of them.

The significance of the above described apparatus is that with each clock pulse a decompressed code is achieved. Although an extra clock pulse is used to remove the data, the system 40 both enters a compressed data code from the shift register 42 and outputs a decompressed code at output 49 with every clock pulse. This is a significant improve¬ ment over the sequential method of the prior art.

It is noted that since the number of minterms in the PLA 44 is rather large (256) , a significant load may be placed on the output. Two methods may be utilized to overcome this. In a first, the PLA 44 is divided into a larger number of smaller PLAs with the appropriate combina¬ tional logic. In a second, the transistors which make up the PLA 44 are precharged, which results in faster signal processing and less load at the output. Both of these procedures are well known in the art and can be combined together.

The foregoing descriptions of specific embodiments of the present invention have been presented for purposes of illustration and description. They are not intended to be exhaustive or to limit the invention to the precise forms disclosed, and obviously many modifications and variations are possible in light of the above teaching. The embodi¬ ments were chosen and described in order to best explain the principles of the invention and its practical appliσa- tion, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use con-

templated. It is intended that the scope of the invention be defined by the Claims appended hereto and their equivalents.