Title:
HV-SOI LDMOS DEVICE WITH INTEGRATED DIODE TO IMPROVE RELIABILITY AND AVALANCHE RUGGEDNESS
Document Type and Number:
WIPO Patent Application WO2003003464
Kind Code:
A3
Abstract:
A hybrid semiconductor device is presented in which one or more diode regions are integrated into a transistor region. In a preferred embodiment the transistor region is a continuous (self-terminating) SOI LDMOS device in which are integrated one or more diode portions. Within the diode portions, since there is only one PN junction, the mechanism for breakdown failure due to bipolar turn-on is nonexistent. The diode regions are formed such that they have a lower breakdown voltage than the transistor region, and thus any transient voltage (or current) induced breakdown is necessarily contained in the diode regions. In a preferred embodiment, the breakdown voltage of the diode portions is lowered by narrowing their field plate length relative to the transistor portion of the device. This allows the device to survive any such breakdown without being destroyed, resulting in a more rugged and more reliable device.
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Inventors:
PETRUZZELLO JOHN
LETAVIC THEODORE J
SIMPSON MARK R
LETAVIC THEODORE J
SIMPSON MARK R
Application Number:
PCT/IB2002/002414
Publication Date:
November 27, 2003
Filing Date:
June 20, 2002
Export Citation:
Assignee:
KONINKL PHILIPS ELECTRONICS NV (NL)
International Classes:
H01L21/762; H01L21/822; H01L21/8234; H01L27/04; H01L27/06; H01L27/08; H01L27/088; H01L27/12; H01L29/40; H01L29/78; H01L29/786; H01L29/861; (IPC1-7): H01L27/02; H01L27/12; H01L29/06
Foreign References:
| FR2754406A1 | 1998-04-10 | |||
| US5767550A | 1998-06-16 | |||
| US5468984A | 1995-11-21 |
Other References:
CORNEL, M.E. AT AL: "Impact ionization in saturated high-voltage LDD lateral DMOS FETs", PROCEEDINGS OF THE 3RD INTERNATIONAL SYMPOSIUM ON POWER SEMICONDUCTOR DEVICES AND ICS, 22 April 1991 (1991-04-22) - 24 April 1991 (1991-04-24), Baltimore, MD, USA, pages 164 - 167, XP002253260
CONTI F ET AL: "SURFACE BREAKDOWN IN SILICON PLANAR DIODES EQUIPPED WITH FIELD PLATE", SOLID STATE ELECTRONICS, ELSEVIER SCIENCE PUBLISHERS, BARKING, GB, vol. 15, 1972, pages 93 - 105, XP000915334, ISSN: 0038-1101
YAMAGUCHI H ET AL: "200 V RATING CMOS TRANSISTOR STRUCTURE WITH INTRINSIC SOI SUBSTRATE", IEICE TRANSACTIONS ON ELECTRONICS, INSTITUTE OF ELECTRONICS INFORMATION AND COMM. ENG. TOKYO, JP, vol. E83-C, no. 12, December 2000 (2000-12-01), pages 1961 - 1967, XP001059318, ISSN: 0916-8524
SANG-KOO CHUNG ET AL.: "Analytical model for the surface field distribution of SOI RESURF devices", IEEE TRANSACTIONS ON ELECTRON DEVICES, vol. 45, no. 6, 1998, USA, pages 1374 - 1376, XP002253280
CONTI F ET AL: "SURFACE BREAKDOWN IN SILICON PLANAR DIODES EQUIPPED WITH FIELD PLATE", SOLID STATE ELECTRONICS, ELSEVIER SCIENCE PUBLISHERS, BARKING, GB, vol. 15, 1972, pages 93 - 105, XP000915334, ISSN: 0038-1101
YAMAGUCHI H ET AL: "200 V RATING CMOS TRANSISTOR STRUCTURE WITH INTRINSIC SOI SUBSTRATE", IEICE TRANSACTIONS ON ELECTRONICS, INSTITUTE OF ELECTRONICS INFORMATION AND COMM. ENG. TOKYO, JP, vol. E83-C, no. 12, December 2000 (2000-12-01), pages 1961 - 1967, XP001059318, ISSN: 0916-8524
SANG-KOO CHUNG ET AL.: "Analytical model for the surface field distribution of SOI RESURF devices", IEEE TRANSACTIONS ON ELECTRON DEVICES, vol. 45, no. 6, 1998, USA, pages 1374 - 1376, XP002253280
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