Title:
HYBRID CLOCKING SCHEME FOR TRANSMITTING PACKETIZED AUDIO AND POWER OVER A COMMON CONDUCTOR
Document Type and Number:
WIPO Patent Application WO/2022/081412
Kind Code:
A3
Abstract:
A distributed amplification and packetized audio transmission system for clock synchronization and alignment between an audio/power source and endpoints with dedicated amplifiers and speakers. An Ethernet audio signal is combined with a Power-Line Communications (PLC) signal for transmission from the source to the endpoints over a common conductor. A single master clock in the source synchronizes the Ethernet audio transmitter with the PLC transmitter. Each end-point has a PLC receiver to recover the master clock for use by its Ethernet audio receiver to provide reliable clock synchronization between the source clock and the endpoint clocks. The endpoints can adjust and re-timestamp the PTP packetized clock based upon symbol and timing information from the PLC receiver.
Inventors:
BUTLER JOEL (US)
SOMMERFELD JEREMY (US)
SOMMERFELD JEREMY (US)
Application Number:
PCT/US2021/053960
Publication Date:
June 16, 2022
Filing Date:
October 07, 2021
Export Citation:
Assignee:
DOLBY LABORATORIES LICENSING CORP (US)
International Classes:
H04B3/54; H04H20/00; H04J3/06
Domestic Patent References:
| WO2003042858A1 | 2003-05-22 | |||
| WO2016160876A1 | 2016-10-06 |
Foreign References:
| US20060072695A1 | 2006-04-06 | |||
| US20050015805A1 | 2005-01-20 |
Other References:
HENRY MICKAËL ET AL: "Setup and First Experimentation Over an AES67 Over 802.11 Network", JAES, AES, 60 EAST 42ND STREET, ROOM 2520 NEW YORK 10165-2520, USA, 10 March 2019 (2019-03-10), XP040706579
Attorney, Agent or Firm:
ANDERSEN, Robert L. et al. (US)
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