[0001] This PCT International Application claims priority to, and the benefit of, U.S. Provisional Patent Application No. 63/311,623, filed February 18, 2022, entitled “BROADBAND ULTRA-COMPACT HIGH-LINEARITY HYBRID N/PMOS BIDIRECTIONAL AMPLIFIER,” which is hereby incorporated by reference in its entirety.

Background

[0002] The continuous growth of data rates has stimulated the rapid development of 5G New Radio (NR) in the mm-wave FR2 bands (above 24GHz). Consequently, to compensate for the mm-wave high path loss, large-scaled MIMO arrays have become essential. This calls for compact, high-performance mm-wave 5G front-end electronics to integrate many MIMO channels on the same chip for low cost and low form factor.

[0003] A challenge for mm-wave 5G MIMOs is to integrate both front-end transmitter (TX) and receiver (RX) chains in each array pixel with a minimum silicon area to form a co- apertured low-cost array. The conventional TX and RX architecture often consists of a PA and an LNA placed in a parallel configuration and combined by a T/R switch to control the TX/RX mode for a single-phase array element. While this topology makes the design more modular, e.g., to be allocated to different design teams, it results in increased chip area due to many separate matching networks for the PA/LNA/switch, as well as results in the introduction of switching loss that can degrade the PA output power (Pout) and LNA noise figure (NF), particularly at higher frequencies.

[0004] While bi-directional mm-wave front-ends are gaining popularity, existing designs only provide for narrow bandwidth and very limited PA Pout and efficiency.

[0005] There is a benefit to improving front-end transmitters (TX) and receivers (RX) for phase array antennas and various electric circuitries.

Summary

[0006] An exemplary complementary bi-directional amplifier (e.g., for 5G wireless systems in RF and mm-Wave frequencies) and methods are disclosed that employ an integrated front-end transmitter (TX) and receiver (RX) chains in each array pixel (or antenna) that can employ minimum silicon area or package area to form a co-apertured low-cost array. The exemplary complementary bi-directional amplifier addresses integration issue and can provide a system with broad operation bandwidth, ultra-compactness, high linearity, low noise, and high efficiency at both RF and mm-Wave frequencies for both small-signal and large-signal operations.

[0007] In some embodiments, the exemplary bi-directional amplifier includes a shared PA/LNA matching network that can improve the front-end performance while also obviating the T/R switch. The exemplary bi-directional amplifier may employ a hybrid NMOS/PMOS (also referred to herein as N/PMOS), among other topologies, that may allow for the PA deep Class- AB biasing and device cascode, which can substantially increase PA Pout and efficiency.

[0008] In an aspect, a device (e.g., a RADAR array system, RF array system, a satellite payload system, a satellite ground terminal, a 5G and/or mmWave base station, a 5G or mmWave handset, frond-end circuit) comprising a complementary bi-directional PA/LNA circuit (e.g., front-end module (FEM)) comprising: a first amplifier portion having a first set of transistors associated with a first device type; and a second amplifier portion having a second set of transistors associated with a second device type complementary to the first set of transistors, wherein the first amplifier portion is configured to operate as a driver amplifier and/or a power amplifier, and wherein the second amplifier portion is configured to operate as a low noise amplifier and/or its buffer amplifier.

[0009] In some embodiments, the device further includes (i) a shared PA/LNA matching network (e.g., a distributed balun) coupled to unified LNA input/PA output of the complementary bi-directional PA/LNA circuit or (ii) a multi-port network.

[0010] In some embodiments, the complementary bi-directional PA/LNA includes an integrated front-end transmitter (TX) and receiver (RX) chain.

[0011] In some embodiments, the complementary bi-directional PA/LNA is configured for PA deep Class- AB biasing and device cascode topology.

[0012] In some embodiments, the first amplifier stage includes a PMOS transistor stage configured to operate as the low noise amplifier and/or its buffer amplifier, and the second amplifier stage includes an NMOS transistor stage configured to operate as a driver amplifier and/or power amplifier.

[0013] In some embodiments, the first amplifier stage includes an NMOS transistor stage configured to operate as the low noise amplifier and/or its buffer amplifier, and the second amplifier stage includes a PMOS transistor stage configured to operate as a driver amplifier and/or power amplifier.

[0014] In some embodiments, the complementary bi-directional PA/LNA circuit further includes a third amplifier portion having a third set of transistors associated with the first device type; and a fourth amplifier portion having a fourth set of transistors associated with a second device type complementary to the first set of transistors, wherein the first amplifier portion, the second amplifier portion, the third amplifier portion, and the fourth amplifier portion are connected through one or several multi-port networks (e.g., inter-stage matching network).

[0015] In some embodiments, the broadband high-linearity complementary bi-directional PA/LNA circuit further includes a third amplifier portion having a third set of transistors associated with the second device type; and a fourth amplifier portion having a fourth set of transistors associated with a second device type complementary to the first set of transistors, wherein the first amplifier portion, the second amplifier portion, the third amplifier portion, and the fourth amplifier portion are connected through one or several multi-port networks (e.g., interstage matching network).

[0016] In some embodiments, the third amplifier portion and the fourth amplifier portion are connected through a multi-port network (e.g., inter-stage matching network).

[0017] In some embodiments, the first amplifier portion and the second amplifier portion are connected via DC connections.

[0018] In some embodiments, the first amplifier portion and the second amplifier portion are connected through a coupling selected from the group consisting of electrically DC coupled, electrically AC coupled, magnetically coupled, EM coupled, or a combination thereof.

[0019] In another aspect, a device (e.g., a RADAR array system, RF array system, a satellite payload system, a satellite ground terminal, a 5G and/or mmWave base station, a 5G or mmWave handset, frond-end circuit) comprising: a complementary bi-directional beamformer circuit (e.g., front-end module (FEM)) comprising: a first beamformer portion having a first set of transistors associated with a first device type; and a second beamformer portion having a second set of transistors associated with a second device type complementary to the first set of transistors, wherein the first beamformer portion is configured to operate as a transmitter (Tx) chain or a portion thereof; and wherein the second amplifier portion is configured to operate as receiver (Rx) chain or a portion thereof. [0020] In some embodiments, the complementary bi-directional beamformer circuit includes an up-down converter or a complementary bi-directional up-down converter.

[0021] In some embodiments, the complementary bi-directional beamformer circuit includes a phase shifter or a complementary phase shifter.

[0022] In some embodiments, the complementary bi-directional beamformer circuit includes one or multiple up-down converters or one or multiple complementary bi-directional up-down converters.

[0023] In some embodiments, the complementary bi-directional beamformer circuit includes one or multiple phase shifters or one or multiple complementary bi-directional phase shifters.

[0024] In some embodiments, the complementary bi-directional beamformer circuit includes one or multiple filters or one or multiple complementary bi-directional filters.

[0025] In some embodiments, the complementary bi-directional beamformer circuit includes one or multiple buffers or one or multiple complementary bi-directional buffers.

[0026] In another aspect, a device is disclosed comprising a complementary bidirectional circuit comprising: a first device bi-directional portion having a first set of transistors associated with a first device type for a first electric circuit; and a second device bi-directional portion having a second set of transistors associated with a second device type complementary to the first set of transistors for a second electric circuit, wherein the complementary bi-directional circuit is configured as a buffer or a filter.

[0027] In some embodiments, the device includes the features of any one of the abovediscussed devices.

[0028] In some embodiments, the above-discussed devices having (i) the first amplifier portion and the second amplifier portion, (ii) the first beamformer portion and the second beamformer portion, or (iii) the first device bi-directional portion and the second device bidirectional portion, are connected via DC connections.

[0029] In some embodiments, the above-discussed devices having (i) the first amplifier portion and the second amplifier portion, (ii) the first beamformer portion and the second beamformer portion, or (iii) the first device bi-directional portion and the second device bidirectional portion, are connected through a coupling selected from the group consisting of electrically DC coupled, electrically AC coupled, magnetically coupled, EM coupled, or a combination thereof.

[0030] In some embodiments, the above-discussed devices having the complementary bidirectional PA/LNA circuit, the complementary bi-directional beamformer circuit, or the complementary bi-directional circuit, are connected to a first antenna array element.

[0031] In some embodiments, the above-discussed devices having the complementary bidirectional PA/LNA circuit, the complementary bi-directional beamformer circuit, or the complementary bi-directional circuit, are connected to a set of two or more antenna array elements.

[0032] In some embodiments, the above-discussed devices having the complementary bidirectional PA/LNA circuit, the complementary bi-directional beamformer circuit, or the complementary bi-directional circuit, are connected to the one or multiple feeds of a polarized antenna array element.

[0033] In some embodiments, the above-discussed device having the complementary bidirectional PA/LNA circuit, the complementary bi-directional circuit, or the complementary bidirectional beamformer circuit, includes: NMOS/PMOS devices, NPN/PNP bipolar devices, gallium nitride (GaN) devices, gallium arsenide (GaAs) devices, carbon nanotubes, graphene devices, or a combination thereof.

[0034] In some embodiments, the above-discussed device having the complementary bidirectional PA/LNA circuit, the complementary bi-directional beamformer circuit, or the complementary bi-directional circuit, is configured to operate by an adjustment of a biasing current (e.g., using tail current sources) and/or a biasing voltage.

[0035] In another aspect, a method is disclosed comprising providing the abovediscussed device having the hybrid N/PMOS bi-directional PA/LNA circuit comprising a first amplifier portion having a first set of transistors associated with a first device type; and a second amplifier portion having a second set of transistors associated with a second device type complementary to the first set of transistors, wherein the first amplifier portion is configured to operate as a driver amplifier and/or a power amplifier, wherein the second amplifier portion is configured to operate as a low-noise amplifier and/or its buffer amplifier; actuating the first amplifier portion configured as the driver amplifier and/or the power amplifier with a first signal to transmit the signal over an antenna or antenna array; and actuating the second amplifier portion configured as the low noise amplifier and/or its buffer amplifier to receive a second signal over the antenna or antenna array.

[0036] In another aspect, a method is disclosed comprising providing the abovediscussed device having the complementary bi-directional beamformer circuit; actuating the first beamformer portion to transmit a signal over the transmitter (Tx) chain; and actuating the second beamformer portion to receive a signal over the receiver (Rx) chain.

[0037] In another aspect, a method is disclosed comprising providing the abovediscussed device having the complementary bi-directional circuit; actuating the first device bidirectional portion to provide a buffer, filter, or driver operation for the first electric circuit; and actuating the second device bi-directional portion to provide a buffer, filter, or driver operation for the second electric circuit.

[0038] In some embodiments, the device and/or circuit configuration is achieved by adjusting the biasing currents (e.g., using tail current sources) or the biasing voltages.

Brief Description of the Drawings

[0039] The following detailed description of specific embodiments of the disclosure will be better understood when read in conjunction with the appended drawings. For the purpose of illustrating the disclosure, specific embodiments are shown in the drawings. It should be understood, however, that the disclosure is not limited to the precise arrangements and instrumentalities of the embodiments shown in the drawings.

[0040] Figs. 1A, IB, and 1C each show an exemplary antenna module system configured with a hybrid complementary bi-directional PA/LNA-circuit configured with one or more hybrid complementary amplifier stages 104 in accordance with an illustrative embodiment.

[0041] Figs. 2A, 2B, and 2C show an example of the complementary bi-directional PA/LNA device configured with a broadband high-linearity hybrid NMOS transistor stage and a PMOS transistor stage and its associated operation in accordance with an illustrative embodiment.

[0042] Fig. 3 A shows the schematic of an example of the exemplary hybrid complementary bi-directional PA/LNA 100 configured with two sets of the hybrid N/PMOS bidirectional PA/LNA amplifier stages 104, as examples of multi-stage hybrid N/PMOS bidirectional devices. [0043] Fig. 3B also shows the corresponding die-micrograph for the exemplary complementary bi-directional PA/LNA of Fig. 3 A implemented in 45nm CMOS SOI.

[0044] Figs. 3C and 3D each show simulation performance results of the exemplary complementary bi-directional PA/LNA of Fig. 3 A.

[0045] Figs. 4A, 4B, 4C, 4D, and 4E shows additional examples of a single-stage or multi-stage complementary bi-directional PA/LNA-circuit, e.g., of Fig. 1A, in accordance with various illustrative embodiments.

[0046] Fig. 5A and 5B each show an example type of coupling between the complementary devices of the bi-directional circuit in accordance with an illustrative embodiment.

[0047] Figs. 6A, 6B, 6C, 6D, and 6E each show an example type of antenna and antenna array and its respective interface with the complementary devices of the bi-directional circuit. [0048] Figs. 7A and 7B each show an example configuration of the complementary bidirectional circuit for other applications.

[0049] Figs. 8A, 8B, 8C, 8D, 8E, and 8F show various aspects of measurement results and associated measurements performed during the study in the development and evaluation of the hybrid complementary bi-directional PA/LNA and/or amplifiers described herein.

Detailed Specification

[0050] To facilitate an understanding of the principles and features of various embodiments of the present invention, they are explained hereinafter with reference to their implementation in illustrative embodiments.

[0051] Some references, which may include various patents, patent applications, and publications, are cited in a reference list and discussed in the disclosure provided herein. The citation and/or discussion of such references is provided merely to clarify the description of the present disclosure and is not an admission that any such reference is “prior art” to any aspects of the present disclosure described herein. In terms of notation, “[n]” corresponds to the nth reference in the list. All references cited and discussed in this specification are incorporated herein by reference in their entirety and to the same extent as if each reference was individually incorporated by reference.

[0052] Example Systems [0053] Figs. 1A-1C each show an exemplary antenna module system 100 (shown as 100a, 100b, 100c) configured with hybrid bi-directional PA/LNA-circuit 102 (shown as bidirectional PA/LNA “1” 102a, “2” 102b . . . “N” 102N) configured with one or more hybrid complementary amplifier stages 104 (e.g., broadband high-linearity hybrid complementary amplifier stages) in accordance with an illustrative embodiment. The term “hybrid” refers to the bi-directional circuit (e.g., PA/LNA-circuit) having both a type-1 device (e.g., NMOS or PMOS) and a type-2 device (e.g., PMOS or NMOS) complementary to the type-1 device. In Fig. 1 A, the exemplary antenna module system 100a is configured to drive and receive signals from a 5G or mmWave phased array antenna module. In Fig. IB, the exemplary antenna module system 100b is configured to drive and receive signals from an RF-phased array antenna. In Fig. 1C, the exemplary system 100c is configured to drive and receive signals as a beamformer.

[0054] 5G and/or mmWave Application. In the example shown in Fig. 1 A, the exemplary 5G or mmWave antenna module system 100a includes a 5G or mmWave phased array antenna module 106 (shown having element “1” 106a, element “2” 106b, . . ., element “N” 106n) and associated circuitries, including a power amplifier and low noise amplifier (show as hybrid bidirectional PA/LNA) and other 5G or mmWave front-end circuitries 108 (shown as mmWave Front-End “1” 108a, Front-End “2” 108b . . ., Front-End “N” 108n), e.g., implemented in a frontend module 105. In the example shown in Fig. IB, the same or similar broadband high-linearity hybrid complementary stages 104 are shown for an RF antenna module system 100b.

[0055] Channel 110 (also shown as 110’) shows the front-end components 111 (shown as 111’) and the complementary bi-directional PA/LNA-circuit 102 (shown as 102’) formed of two more hybrid complementary devices 104 (shown as “Amplifier 1 with Device Type 1” 104a and “Amplifier 2 with Device Type 2” 104b) and a set of shared matching networks 112 for a phased array element 106 (shown as 106’). In the example shown in Fig. 1 A, Amplifier 2 with Device Type 2 (104b) is configured to operate as the low noise amplifier for the antenna array element 106’, and Amplifier 1 with Device Type 1 (104a) is configured to operate as the driving low noise amplifier for the antenna array element 106’. Amplifier 1 with Device Type 1 (104a) and Amplifier 2 with Device Type 2 104b are shown connected to other front-end circuitries 108’ (e.g., mixer, modulators, etc., conventional or otherwise for frond-end circuitries).

[0056] The hybrid complementary bidirectional PA/LNA 102 is configured to operate in the PA mode and the LNA mode via actuation of the transistor stages 104 without the need for a T/R switch (employed in conventional front-end circuits). In the PA mode, the second transistor stage 104b may be set to “ON” while the first transistor stage 104a would be “OFF” (opposite or complementary to the PMOS transistor stage 104b). In the LNA mode, the first transistor stage 104a may be set to “ON” while the second transistor stage lOba would be “OFF” (opposite or complementary to the NMOS transistor stage 104a).

[0057] RF Application. In Fig. IB, the exemplary RF antenna module system 100b includes an RF phased array antenna module 106 (shown having element “1” 106a’, element “2” 106b’, . . . element “N” 106n’) and associated circuitries, including a power amplifier and low noise amplifier (show as the complementary bidirectional PA/LNA) and other RF front-end circuitries 109 (shown as RF Front-End “1” 109a, Front-End “2” 109b ..., Front-End “n” 109n). In the example shown in Fig. IB, the same or similar hybrid complementary bidirectional PA/LNA 104 is shown for an RF antenna module system 100b.

[0058] The term “RF” can refer to any radiofrequency communication or applications described herein, e.g., 5G and/or mm-Wave, e.g., having a frequency between 24 GHz and 40 GHz. RF can also include application domains having a frequency greater than 40 GHz, e.g., up to 50 GHz, up to 55 GHz, up to 60 GHz, up to 65 GHz, up to 70 GHz, etc. The term “RF” can also refer to frequencies for RADAR application, among other applications described herein.

[0059] Example Circuit Implementation and Method of Operation of the Exemplary Hybrid N/PMOS Bi-Directional PA/LNA

[0060] Fig. 2A shows an example of a complementary bi-directional PA/LNA device (e.g., 102) configured with an NMOS transistor stage (e.g., 104a) (shown as 104a’) and a PMOS transistor stage (e.g., 104b) (shown as 104b’) in accordance with an illustrative embodiment.

[0061] Conventional cores 202 (see Fig. 2C) typically use only NMOS devices (shown as 204). When in the PA mode, MPA devices (206’) are “ON,” and MLNA devices (208’) are “OFF,” as controlled by their tail switches. The parasitic capacitances C _g d of the OFF-MLNA devices serve as the neutralization capacitors for the PA device, MPA. The LNA mode operates in a similar way. However, this conventional design can exhibit limitations on its device-gate biasing, output voltage swing, and impedance transformation. In the example shown in Fig. 2C, with VDD = IV, in the PA-mode, the desired output voltage swing is close to 2V single-ended (Vx) (209a) limited by the device knee voltage if the MPA devices gates are biasing close to VT, e.g., 0.3 V for high-efficiency deep Class-AB operation. Therefore, the gate voltage VGS 211 of the LNA device, MLNA, exceeds the voltage threshold VT for an extended period, and the “OFF” LNA devices can turn “ON” undesirably.

[0062] Consequently, a short “ON” resistance could form a shunt between the differential MPA devices gate, degrading Pout, efficiency, and linearity. Thus, conventional NMOS bidirectional designs (e.g., 202) would inevitably have to increase their PA-device gate voltage VGS to the Class-A mode (e.g., 0.7V) to prevent the MLNA devices 208’ from turning “ON” undesirably. Moreover, the LNA devices MLNA and gate may reduce, i.e., the low VDD supply for the PA mode. The combined effects can result in poorer or poor PA performance with low or lower Pout and efficiency as compared to the exemplary complementary bi-directional PA/LNA core that utilizes a hybrid N/PMOS.

[0063] Also, high-performance front-end circuitries typically adopt a lower PA load impedance than the LNA source impedance. Sharing the same or common matching network interfacing with the antenna would force the same impedance for the PA load and LNA source, which would further degrade the front-end performance for the conventional bi-directional PA/LNA topology.

[0064] Referring to Fig. 2B, the exemplary hybrid complementary bi-directional PA/LNA core 102, reproduced from Fig. 2 A, in contrast to the conventional bi-directional PA/LNA, utilizes complementary device types (comprising N/PMOS, shown as NMOS 210 and PMOS 212) in combination with a cascode topology in which the hybrid N/PMOS can be actuated between the PA mode and the LNA mode. When the PMOS transistors (shown as 212a, 212b) operate as the LNA device MLNA (208) (see diagram 220), the NMOS transistor (shown as 210a, 210b) are kept in the “OFF” state even if the gate voltage VGS of the LNA device MLNA exceeds VT. Consequently, the parasitic “OFF” capacitance of the LNA device MLNA 208 can serve as the neutralization capacitors (222) between the gate and drain of the PA device MPA 206. Thus, the gates of PA device MPA 206 can be biased close to its Vrfor deep Class-AB operation.

[0065] When in the PA mode (see diagram 224), the MPA devices (206) are “ON,” and MLNA devices (208) are “OFF,” as controlled by their tail switches. The parasitic capacitances C _g d (226) of the OFF -MLNA devices (208) serve as the neutralization capacitors for the PA device, MPA (206). [0066] Compared to the conventional bi-directional amplifier (e.g., 202, Fig. 2C), the exemplary hybrid N/PMOS bi-directional PA/LNA (e.g., 102) amplifier, for the similar configurations of the two circuits shown in Fig. 2C, can improve the saturated output power (PSAT) by about 2 dB and efficiency by about 25%. The size of the PA/LNA core transistor (206, 208) can be further optimized to match the impedance and reactance values of the load-pull simulation results similar to those of the optimum noise source simulation results. Indeed, in the exemplary complementary bi-directional operation, passive elements can be shared in each mode without the need for the T/R switches that would otherwise affect output power and noise figure performance.

[0067] Plot 214 (see Fig. 2A) shows large-signal simulation results (216 and 218, respectively) for the conventional bi-directional amplifier device core (e.g., 202) and the hybrid N/PMOS bi-directional PA/LNA device core (e.g., 102) with lossless passives. The plot shows the noted improvement in the saturated output power (PSAT) (217a) by about 2 dB (from 16.7 dB to 18.4 dB) and the noted improvement in the efficiency (217b) by about 25% from 33.5% to 58.1%.

[0068] Similar methods of operation of the complementary bi-directional devices may be performed for the complementary bi-directional beamformer and complementary bi-directional circuit, as well as other circuits described herein.

[0069] Example Circuit Implementation and Method of Operation for Another Exemplary Hybrid N/PMOS Bi-Directional PA/LNA

[0070] Fig. 3 A shows a schematic of an example of the exemplary hybrid complementary bi-directional PA/LNA 100 (shown as 300) configured with two sets of the hybrid N/PMOS bi-directional PA/LNA amplifier stages 104 (shown as sets 302, 304), as an example of multi-stage hybrid N/PMOS bi-directional devices. In the example shown in Fig. 3A, the exemplary hybrid complimentary bi-directional PA/LNA 300 includes a driver amplifier 302 and a power/low-noise amplifier (304) that are coupled by a transformer in which the passive elements of the transformers 305a, 305b and the distributed balun 307 for each stage matching networks are shared in the PA-mode and LNA-mode.

[0071] In the example shown in Fig. 3A, in the PA mode, the NMOS transistors, as an example of the first amplifier (e.g., 104a) (shown as 306 and 306’) of the hybrid N/PMOS bi- directional PA/LNA amplifier stages (302, 304) may be characterized as a common-source (CS)- topology driver amplifier (see 302) and a cascade-topology power amplifier (see 304).

[0072] And, in the LNA mode, using PMOS transistors, as an example of the second amplifier (e.g., 104b) (shown as 308 and 308’) of the hybrid N/PMOS bi-directional PA/LNA amplifier stages (302, 304) may be characterized as a CS-topology driver amplifier (see 302) and a CS-topology low-noise amplifier (see 304).

[0073] In the example shown in Fig. 3 A, the hybrid N/PMOS bi-directional PA/LNA amplifier stages (302, 304) include de-Q resistors (shown as “Rl”, “R2”, “R3” 310) and capacitors (shown as “C4” 312) that are configured to improve the flatness of the gain and match the performance in each mode. In this example, MOSFET switches 314 (shown as 314a, 314b, 314c, 314d) are employed to control the “ON/OFF” states in both modes. In the PA mode, the LNA PMOS transistors (308) are turned “OFF,” and the PMOS parasitic capacitors Cgd (previously shown in Fig. 2B) are used as capacitance for neutralization in the differential amplifier. And, in the LNA mode, the PA NMOS transistors (306) are turned “OFF” and neutralize the LNA PMOS differential amplifier. In this example, the LNA of the PA/LNA stage includes small transistors (e.g., 308) for optimizing the noise figure and minimal parasitic effects, and the PA uses a large transistor (e.g., 306) for sufficient power capacity. An additional capacitor (shown as Cneu 316) is included that is configured to compensate for the Cgd imbalance caused by the different transistor sizes. In the exemplary topology, the transistor of the commongate stage in the PA mode can operate as a switch in the LNA mode.

[0074] As the switch (314c) operates, a parasitic “ON” resistance (“R3” 310) is introduced to the LNA input. The insertion loss of the ON resistance, in this example, could be observed to be 1.2dB at 28GHz and 1.9dB at 37GHz from the example simulation results, and the insertion loss contributes to the LNA-mode performance.

[0075] In the example shown in Figs. 3 A and 3B, the exemplary hybrid complementary bi-directional PA/LNA 100 includes wideband matching networks (305a, 305b) for the output network of the PA-mode and the input network of the LNA-mode as well as the distributed balun 307 that may be designed according to the device-capacitance (Cdev) value that satisfies both the PA-mode load-pull simulation result and the LNA-mode optimum-noise source-pull result. The distributed balun, in this example, has a passive efficiency of > 85% and an insertion loss of > 0.8dB at 23.8 to 45.1GHz based on simulation results. [0076] Fig. 3B also shows the corresponding die-micrograph for the exemplary complementary bi-directional PA/LNA of Fig. 3 A implemented in 45nm CMOS SOI. In the example, the hybrid complementary bi-directional PA/LNA 100 includes wideband matching networks 305a and 305b (shown as 305a’, 305b’) for the input network of the PA mode and the output network of the LNA mode as well as the distributed balun 307 (shown as 307’). The exemplary complementary bi-directional PA/LNA occupies a core area of 720pm x 260pm and the total chip area, including bond pads, of 850pm x 700pm.

[0077] Fig. 3C shows the simulation performance results of the exemplary complementary bi-directional PA/LNA of Fig. 3 A. The simulations are performed at 28GHz for the PA/LNA core for both the PA mode and the LNA mode. In the PA mode, the results show a max OPidb of 19 dB with 0.5 dB steps and a max PAEpidb of 55% with 5% steps. The parameters employed in the simulations are shown in table 318.

[0078] Fig. 3D shows 3D EM simulations of the distributed balun 307’ (shown as 307”) PA/LNA matching network of the output stage. The results show greater than 85% efficiency between 20 and 45 GHz and an insertion loss that is greater than -0.8 dB between 23.8 GHz and 47.2 GHz.

[0079] Similar methods of operation of the complementary bi-directional devices may be performed for the complementary bi-directional beamformer and complementary bi-directional circuit, as well as other circuits described herein.

[0080] Additional Examples of Multiple-Stage Hybrid N/PMOS Bi-Directional Devices [0081] Figs. 4A-4E show additional examples of the single-stage or multi-stage complementary bi-directional PA/LNA circuit in accordance with various embodiments.

[0082] Single Complementary Bi-Directional PA/LNA-Circuit. In the example shown in Fig. 4A, the complementary bi-directional PA/LNA-circuit 102 (shown as 400a) of Fig. 1A has a complementary amplifier stage 104 configured with NMOS-type transistors 402 and PMOS-type transistors 404. As noted, the complementary bi-directional PA/LNA circuit may employ NMOS/PMOS devices, NPN/PNP bipolar devices, gallium nitride (GaN) devices, gallium arsenide (GaAs) devices, carbon nanotubes, graphene devices, or a combination thereof. Also, the devices may be fabricated as CMOS (complementary metal-oxide semiconductor), bi-polar junction transistors (BJT), field-emitting transistors (FET), etc. [0083] In the example shown in Fig. 4A, the NMOS-type transistors 402 and PMOS-type transistors 404 are connected at their respective input and output to a respective multi-port network (shown as 406a, 406b) or other types of shared matching circuits described herein. An example of a multi-port network may include a multi-port coupler, a multi-coil coupler, or a multi-coil transformer. The multi-port network may include 2, 3, 4, 5, or 6 coils, couplers, transformers, or any other configurations described or referenced herein.

[0084] Similar configurations and methods of operation may be performed for the complementary bi-directional beamformer and complementary bi-directional circuit, as well as other circuits described herein.

[0085] Multi-Stage Complementary Bi-Directional PA/LNA-Circuit #1. In the example shown in Fig. 4B, the complementary bi-directional PA/LNA-circuit 102 (shown as 400b) includes a multiple-stage complementary amplifier configured with two sets of complementary amplifiers. In Fig. 4B, the first set 408 of complementary amplifiers includes the NMOS-type transistors 402 and PMOS-type transistors 404, and a second set 410 of complementary amplifiers includes the NMOS-type transistors 412 and PMOS-type transistors 414. The first set 408 of complementary amplifiers (402, 404), and the second set 410 of complementary amplifiers (412, 414) are connected through a multi-port network 416 (shown as 416c). The inter-stage multi-port network 416 may include a multi-port coupler, a multi-coil coupler, or a multi-coil transformer, e.g., having 2, 3, 4, 5, 6 coils, couplers, or transformers, or any other configurations described or referenced herein. An example is also shown and described in relation to Figs. 3 A-3D.

[0086] In some embodiments, the first set 408 of complementary amplifiers is employed as a power amplifier and/or low-noise amplifier, and the second set 410 of the complementary amplifier is employed as a driver amplifier for the power amplifier and/or buffer amplifier for the low-noise amplifier.

[0087] In some embodiments, the first set 408 of complementary amplifiers is employed as a power amplifier and/or low-noise amplifier, and the second set 410 of complementary amplifier is employed as buffers, filters, driver amplifiers, among others described herein for the power amplifier and the low-noise amplifier.

[0088] In some embodiments, the first set 408 of complementary amplifiers is employed as a first beamformer portion and a second beamformer portion for a complementary bi- directional beamformer circuit, and the second set 410 of the complementary amplifier is employed as buffers, filters, driver amplifiers, among others described herein for the first beamformer portion and a second beamformer portion.

[0089] In some embodiments, the first set 408 of complementary amplifiers is employed as a first device bi-directional portion and a second device bi-directional portion for a complementary bi-directional circuit, and the second set 410 of the complementary amplifier is employed as buffers, filters, driver amplifiers, among others described herein for the first device bi-directional portion and a second device bi-directional portion.

[0090] The input of the first set 408 of complementary amplifiers (402, 404) and the output of the second set 410 of complementary amplifiers (412, 414) are connected through a multi-port network (e.g., 416a, 416b). In certain design configurations, the multi-port network (e.g., 416a, 416b) of the input and output of the first set 408 of complementary amplifiers and the second set 410 of complementary amplifiers may be the same. In some embodiments, the multiport network (e.g., 416a, 416b) of the input and output of the first set 408 of complementary amplifiers and the second set 410 of complementary amplifiers may be different. The interstage multi-port network (e.g., 416c) may also be configured to be the same or different from the first input/output multi-port network (e.g., 416a) and/or second input/output multi-port network (e.g., 416b).

[0091] Multi-Stage Complementary Bi-Directional PA/LNA-Circuit #2. Fig. 4C shows another configuration of the multiple-stage complementary bi-directional amplifier configured with two sets of complementary amplifiers. In Fig. 4C, the first set 408 of complementary amplifiers includes the NMOS-type transistors 402 and PMOS-type transistors 404, and the second set 410 of complementary amplifiers includes the NMOS-type transistors 412 and PMOS-type transistors 414. Rather than being connected through a single interstage multi-port network (e.g., 416c) as shown in Fig. 4B, the first set 408 of complementary amplifiers (402, 404) and the second set 410 of complementary amplifiers (412, 414) are connected through a respective multi-port network 416 (shown as 416d and 416e). The inter-stage multi-port network (e.g., 416c) may include a multi-port coupler, a multi-coil coupler, or a multi-coil transformer, e.g., having 2, 3, 4, 5, 6 coils, couplers, or transformers, or any other configurations described or referenced herein. [0092] The input of the first set 408 of complementary amplifiers (402, 404) and the output of the second set 410 of complementary amplifiers (412, 414) are connected through a multi-port network (e.g., 416a, 416b).

[0093] In some embodiments, the first set 408 of complementary amplifiers is employed as a power amplifier and/or low-noise amplifier, and the second set 410 of the complementary amplifier is employed as a driver amplifier for the power amplifier and/or buffer amplifier for the low-noise amplifier.

[0094] In some embodiments, the first set 408 of complementary amplifiers is employed as a power amplifier and/or low-noise amplifier, and the second set 410 of the complementary amplifier is employed as buffers, filters, and driver amplifiers, among others described herein for the power amplifier and the low-noise amplifier.

[0095] In some embodiments, the first set 408 of complementary amplifiers is employed as a first beamformer portion and a second beamformer portion for a complementary bidirectional beamformer circuit, and the second set 410 of the complementary amplifier is employed as buffers and/or filters, driver amplifiers, among others described herein for the first beamformer portion and a second beamformer portion.

[0096] In some embodiments, the first set 408 of complementary amplifiers is employed as a first device bi-directional portion and a second device bi-directional portion for a complementary bi-directional circuit, and the second set 410 of the complementary amplifier is employed as buffers, filters, driver amplifiers, among others described herein for the first device bi-directional portion and a second device bi-directional portion.

[0097] Example Implementation of the Multi-Stage Complementary Bi-Directional PA/LNA-Circuit #1. Fig. 4D shows an example implementation of the multiple-stage complementary amplifier 407 (see 407’ for an example circuit topology) configured with two sets of complementary amplifiers, similar to that shown in Fig. 3 A. The implementation can be characterized as a reduced circuit set for illustrative purposes, but also can operate as a functioning circuit in its own right. In the example shown in Fig. 4D, the two sets of complementary amplifiers include an NMOS/PMOS complementary set (e.g., 402, 404) (also shown as 306’ and 308’) in the first stage 408 and a second NMOS/PMOS complementary set (e.g., 412, 414) (also shown as 306 and 308) in the second stage 410. In the example shown in Fig. 4D, the first stage 408 and the second stage 410 are shown connected via a single interstage multi-port network (shown as 416c) though they can be implemented in other configurations, e.g., as described in relation to Fig. 4C or others described herein.

[0098] The input of the first set 408 of complementary amplifiers (402, 404) and the output of the second set 410 of complementary amplifiers (412, 414) are connected through a multi-port network (e.g., 416a, 416b).

[0099] In some embodiments, the first set 408 of complementary amplifiers is employed as a power amplifier and/or low-noise amplifier, and the second set 410 of the complementary amplifier is employed as a driver amplifier for the power amplifier and/or buffer amplifier for the low-noise amplifier.

[0100] In some embodiments, the first set 408 of complementary amplifiers is employed as a power amplifier and/or low-noise amplifier, and the second set 410 of the complementary amplifier is employed as buffers, filters, and driver amplifiers, among others described herein for the power amplifier and the low-noise amplifier.

[0101] In some embodiments, the first set 408 of complementary amplifiers is employed as a first beamformer portion and a second beamformer portion for a complementary bidirectional beamformer circuit, and the second set 410 of the complementary amplifier is employed as buffers and/or filters, driver amplifiers, among others described herein for the first beamformer portion and a second beamformer portion.

[0102] In some embodiments, the first set 408 of complementary amplifiers is employed as a first device bi-directional portion and a second device bi-directional portion for a complementary bi-directional circuit, and the second set 410 of the complementary amplifier are employed as buffers, filters, driver amplifiers, among others described herein for the first device bi-directional portion and a second device bi-directional portion.

[0103] Example Implementation of the Multi-Stage Complementary Bi-Directional

PA/LNA-Circuit #2. Fig. 4E shows another example implementation of the multiple-stage complementary amplifier 417 (see 417’ for an example circuit topology) configured with two sets of complementary amplifiers, similar to that shown in Fig. 3 A. The implementation can also be characterized as a reduced circuit set for illustrative purposes, but also can operate as a functioning circuit in its own right. In the example shown in Fig. 4E, the two sets of complementary amplifiers include a PMOS/NMOS complementary set (e.g., 422, 424) (shown as 308’ and 306’) in the first stage 418 and a second NMOS/PMOS complementary set (e.g., 426, 428) (shown as 306 and 308) in the second stage 420. In the example shown in Fig. 4E, the first stage 418 and the second stage 420 are also shown connected via a single interstage multiport network (shown as 416c) though they can be implemented in other configurations, e.g., as described in relation to Fig. 4C or others described herein.

[0104] The input of the first set 418 of complementary amplifiers (422, 424) and the output of the second set 420 of complementary amplifiers (426, 428) are connected through a multi-port network (e.g., 416a, 416b).

[0105] Indeed, other configurations of different NMOS or PMOS topologies may be employed in view of these two examples.

[0106] Similar configurations and methods of operation may be performed for the complementary bi-directional beamformer, and complementary bi-directional circuit, as well as other circuits described herein

[0107] Example Coupling of the Complementary Bi-Directional Devices. Fig. 5 A and

Fig. 5B each show an example type of coupling between the complementary devices of the bidirectional circuit. In the example shown in Fig. 5A, a transistor-level implementation is shown for a hardware DC connection. In Fig. 5B, the other type of coupling is shown. Indeed, the coupling may be electrically DC-based coupling, electrically AC -based coupling, magnetic coupling, electromagnetic (EM) based coupling, or a combination thereof.

[0108] Similar configurations and methods of operation may be performed for the complementary bi-directional PA/LNA, complementary bi-directional beamformer, and complementary bi-directional circuit, as well as other circuits described herein.

[0109] Example Antenna Interface with the Complementary Bi-Directional Devices. Figs.

6A, 6B, and 6C each show an example type of antenna and antenna array and its respective interface with the complementary devices of the bi-directional circuit. In the example shown in Fig. 6A, the complementary devices of the bi-directional circuit (e.g., of Fig. 1 A) are shown connected to a single antenna or a single antenna array element of an antenna array. An example interface is shown and described in relation to Fig. 3 A. While the topology is shown for that of Fig. 1 A, the antenna interface may be employed by any of the embodiments described herein, including those described in relation to Figs. 1-5, 6D, and 6E.

[0110] In the example shown in Fig. 6B, the complementary devices of the bi-directional circuit (e.g., of Fig. 1 A) are shown to be connected to at least two antennae or at least two antenna array elements of an antenna array. In the example shown in Fig. 3 A, multiple couplers, coils, or transformers, e.g., as described herein, may be employed to provide connection to the second antenna or the second antenna array elements having two or more feedlines (610, 612). While the topology is shown for that of Fig. 1 A, the antenna interface may be employed by any of the embodiments described herein, including those described in relation to Figs. 1-5, 6D, and 6E.

[OHl] In the example shown in Fig. 6C, the complementary devices of the bi-directional circuit (e.g., of Fig. 1 A and applicable to other configurations described herein) are shown connected at a polarized antenna or a polarized antenna array element of an antenna array. In the example shown in Fig. 3 A, multiple couplers, coils, or transformers, e.g., as described herein, may be employed to provide connection to the polarized antenna or the polarized antenna array elements having two or more feedlines. And, while the topology is shown for that of Fig. 1 A, the antenna interface may be employed by any of the embodiments described herein, including those described in relation to Figs. 1-5, 6D, and 6E.

[0112] Similar configurations and methods of operation may be performed for the complementary bi-directional PA/LNA, complementary bi-directional beamformer, and complementary bi-directional circuit, as well as other circuits described herein.

[0113] Example Shared Matching or Antenna Interface with the Complementary Bi-

Directional Devices. Figs. 6D and 6E each show an example type of antenna and antenna array and its respective interface with the complementary devices of the bi-directional circuit.

[0114] In the example shown in Fig. 6D, the complementary devices of the bi-directional circuit (e.g., of Fig. 1A) are shown connected to a single antenna (e.g., 602) or a single antenna array element of an antenna array through a multi-port network (shown as 618). As described herein, a multi-port network (e.g., 618) may include a multi-port coupler, a multi-coil coupler, or a multi-coil transformer, e.g., having 2, 3, 4, 5, 6 coils, couplers, or transformers, or any other configurations described or referenced herein.

[0115] Fig. 6E shows the complementary devices of the bi-directional circuit (e.g., of Fig. 1 A) connected to a single antenna (e.g., 602) or a single antenna array element of an antenna array through a multi-port coupler (shown as 618). Coils and transformers have winding or bend within them. Couplers are structures that do not have these features. While the topology is shown for that of Fig. 1 A, the antenna interface may be employed by any of the embodiments described herein, including those described in relation to Figs. 1-5, 6D, and 6E.

[0116] Similar configurations and methods of operation may be performed for the complementary bi-directional PA/LNA, complementary bi-directional beamformer, and complementary bi-directional circuit, as well as other circuits described herein.

[0117] Example Complementary Bi-Directional Circuit

[0118] Figs. 7A and 7B each show an example configuration of the complementary bidirectional circuit for other applications. In the example shown in Fig. 7A, the complementary bi-directional circuit may be implemented as a complementary bi-directional buffer 702. In the example shown in Fig. 7B, the complementary bi-directional circuit may be implemented as a complementary bi-directional filter 704.

[0119] The complementary bi-directional buffer 702 may be implemented as a buffer between two circuits 706, 708. The complementary bi-directional filter 704 may be implemented as a low-pass filter, bandpass filter, and high-pass filter. Examples of circuits 706, 708 may include other front-end components, mixers, modulators, etc.). The complementary bidirectional buffers or complementary bi-directional filters may be implementable using the amplifiers, e.g., the broadband high-linearity hybrid N/PMOS stages and various configurations and designs described herein.

[0120] The complementary bi-directional buffer and complementary bi-directional filters may be implemented solely or in combination with any of the other circuits described herein, e.g., the complementary bi-directional PA/LNA and the complementary bi-directional beamformer.

[0121] Example Complementary Bi-Directional Beamformer

[0122] Beamformer Application. Referring back to Fig. 1C, an exemplary beamformer module system 100 (shown 100c) is shown that includes a hybrid complementary beamformer (shown as beamformer “1” 140a, . . . ., beamformer “n” 140b) implemented using the hybrid complementary bi-directional amplifier (e.g., 102) (shown as 142a, 142b, 142c, 142d). Fig. 1C shows four example configurations (shown as 144, 146, 148, and 150) of the beamformer employing the hybrid complementary bi-directional amplifier (e.g., 142a, 142b, 142c, and 142d). In the example configuration 144, the hybrid complementary bi-directional amplifier 142a is shown operating with a hybrid complementary bi-directional up-down converter 152 (shown as 152a) and a hybrid complementary bi-directional phase shifter 154 (shown as 154a). The beamformers (e.g., 140) connect to a phased array 106 (shown as 106a” and 106n”).

[0123] Beamforming operations may be employed to improve the signal -to-noise ratio of received signals, eliminate undesirable interference sources, and focus transmitted signals to specific locations. The exemplary beamforming operations may be employed for sensor or antenna arrays, including MIMO wireless communications systems such as 5G, mmWave, LTE, and WLAN, as well as other RF applications such as RADAR and others described herein.

[0124] In the example shown in Fig. 1C, the hybrid complementary bi-directional amplifier 142a may be configured as a complementary bi-directional amplifier, PA/LNA circuit, hybrid N/PMOS stages, or various configurations described herein. Though shown as interfacing to the hybrid complementary bi-directional up-down converter 152a, the hybrid complementary bi-directional amplifier 142a can alternatively interface to the hybrid complementary bi-directi on phase shifter 154a or other beamformer circuitries.

[0125] The example configurations (e.g., 146, 148, and 150) show different example configurations in which the complementary bi-directional amplifier, PA/LNA circuit, and hybrid N/PMOS stages can be employed.

[0126] In the example configuration 146, the hybrid complementary bi-directional amplifier 142b is shown operating with an up-down converter 152 (shown as 152b) and a hybrid complementary bi-directional phase shifter 154 (shown as 154b).

[0127] In the example configuration 148, the hybrid complementary bi-directional amplifier 142c is shown operating with an up-down converter 152 (shown as 152c) and a phase shifter 154 (shown as 154c).

[0128] In the example configuration 150, the hybrid complementary bi-directional amplifier 142b is shown operating with a hybrid complementary bi-directional up-down converter 152 (shown as 152d) and a phase shifter 154 (shown as 154d).

[0129] Indeed, the sequences of the circuitries in the various examples may be varied and may include additional circuitries.

[0130] Additional Experimental Results and Examples

[0131] A study was conducted to develop and evaluate broadband ultra-compact high- linearity switchless hybrid N/PMOS bi-directional PA/LNA front-end, e.g., for multi-band 5G large-scaled MIMO system [1] and various other applications described herein. The prototyped system includes the hybrid N/PMOS bi-directional PA/LNA front-end, e.g., as described herein in relation to Figs. 1-7.

[0132] The study performed simulations of various circuitries and fabricated corresponding devices. The simulations appear to correspond to the measured results and show a strong efficacy of the hybrid complementary bi-directional amplifier circuits for various RF applications. The experimental results and simulations showed that the hybrid complementary bi-directional amplifier circuits achieved state-of-the-art bi-directional PA/LNA performance, including state-of-the-art bi-directional operation with high linearity and low noise, state-of-the- art broadband operation from 26 to 39GHz and within a compact chip size with no T/R switch. The results suggest the hybrid complementary bi-directional amplifier circuits have great applicability for multi-band 5G large-scaled MIMO systems, among other applications described herein. Figs. 8A, 8B, 8C, 8D, 8E, and 8F show various aspects of measurement results and associated measurements performed during the study in the development and evaluation of the hybrid complementary bi-directional PA/LNA and/or amplifiers described herein.

[0133] PA-mode measurements. Fig. 8A shows the small-signal S-parameters and large- signal continuous-wave (CW) measurement results in the PA-mode, with the measured bias conditions of VGr _x = 0.35V, VGPA = 0.28V, VGCAS = 1.3V, VDDTX = IV, and VDDPA = 2V. In Fig. 8A, it can be observed that the peak gain (S21) has 18.9dB at 27.8GHz with a 3dB bandwidth from 25.3 to 42.0GHz. The input return loss (SI 1) is <10dB from 28.0 to 41.0GHz. At 28GHz, the PA-mode achieved 42.9% PAEpeak with 19.4dBm PSAT and 34.9% PAE at 17.8dBm PldB. At 37GHz, the PA-mode achieves 34.1% PAEpeak with 18.0dBm PSAT and 32.4% PAE at 17.3dBm PldB. Over 26 to 39GHz, the PA-mode achieved > 16.3dBm PldB with > 30.0% PAE at PldB. The PA mode shows a flat PldB of 16.3 to 18.4 dBm and a flat PAE at PldB of 30.0 to 34.9% over 26 to 39GHz, verifying the broadband large-signal matching. Fig. 8C shows an example measurement setup for the PA-mode measurement.

[0134] LNA-mode measurements. Fig. 8B shows the small-signal S-parameters, noise figure, and 2-tone (IIP3) measurement results in the LNA mode, where the measured bias conditions are VDDR _X = VDDLNA = 0V, VGR _X = 0.65V, VGLNA = 0.55V, and VSSR _X = VSSLNA = 1.1V. In Fig. 8B, the peak gain (S21) is 17.6dB at 30.3GHz with a 3dB bandwidth from 27.0 to 38.0GHz. The input return loss (S11) is < 8.6dB from 24.0 to 39.0GHz, and the output return loss (S22) is < lOdB from 26.3 to 42.0GHz. The minimum noise figure (NF) is 5.2dB at 26GHz, and overall NF is < 7.8dB from 24.0 to 40.0GHz. For the 2-tone (IIP3) measurement, two tones with a 100MHz offset are applied to the LNA input over 24.0 to 42.0GHz, respectively. At 28GHz, the LNA-mode achieves -8.6dBm input PidB, 1 l.OdBm PSAT, and 0.9dBm IIP3. At 37GHz, the LNA-mode achieves -7.6dBm input PidB, 10.5dBm PSAT, and 1.4dBm IIP3. Over 26.0 to 39.0GHz, the LNA-mode achieves > -0.9dBm IIP3 and > lOdBm PSAT. Fig. 8C also shows an example measurement setup for the LNA-mode measurement.

[0135] Fig. 8E shows the modulation measurement results using a single-carrier 64- QAM modulation signal. For a 250MSym/s (1.5Gb/s) single-carrier 64-QAM signal, the PA- mode achieved 12.0dBm average Pout (Pavg) and 16.2% average PAE (PAEavg) with -26.2dB rms EVM at 28GHz. At 37GHz, the PA-mode achieved 11 ,4dBm average Pout (Pavg) and 16.7% average PAE (PAEavg) with -24.8dB rms EVM. Fig. 8D shows an example measurement setup for the modulation measurement setup.

Table 1 W 2) [0136] Table 1 shows a performance comparison among prior-art 5G mm-wave bidirectional, uni-directional broadband PA/LNA, and the exemplary hybrid bi-directional PA/LNA. From Table 1, it can be observed that the exemplary hybrid complementary bidirectional PA/LNA demonstrates a broadband and high Pout/efficiency bi-directional mm-wave front-end. Considering that the exemplary design eliminates the T/R switch, where the T/R switch loss is typically IdB in this frequency range [2], the exemplary bi-directional front-end not only achieves competitive performance compared to reported uni-directional designs Fig. 8, but also offers a substantially reduced silicon area.

[0137] Discussion

[0138] The conventional bidirectional amplifier architecture often consists of two antiparallel amplifiers placed together with signal-path switches to control the amplifier mode and directions. Although these conventional topologies improve the design, they increase the chip area by having many separate matching networks for the two amplifiers and switches, as well as the switching loss that degrades the amplifier noise performance, linearity, and output power. On the other hand, though some bi-directional front-ends have been reported, they all use the same type of devices, e.g., NMOS only, that result in degraded large signal performance, narrow bandwidth, and very limited amplifier noise, efficiency, and power capabilities.

[0139] Conclusion

[0140] Some references, which may include various patents, patent applications, and publications, are cited in a reference list and discussed in the disclosure provided herein. The citation and/or discussion of such references is provided merely to clarify the description of the present disclosure and is not an admission that any such reference is “prior art” to any aspects of the present disclosure described herein. In terms of notation, “[n]” corresponds to the n ^th reference in the list. All references cited and discussed in this specification are incorporated herein by reference in their entirety and to the same extent as if each reference was individually incorporated by reference.

[0141] Although example embodiments of the present disclosure are explained in some instances in detail herein, it is to be understood that other embodiments are contemplated. Accordingly, it is not intended that the present disclosure be limited in its scope to the details of construction and arrangement of components set forth in the following description or illustrated in the drawings. The present disclosure is capable of other embodiments and of being practiced or carried out in various ways.

[0142] It must also be noted that, as used in the specification and the appended claims, the singular forms “a,” “an,” and “the” include plural referents unless the context clearly dictates otherwise. Ranges may be expressed herein as from “about” or “ 5 approximately” one particular value and/or to “about” or “approximately” another particular value. When such a range is expressed, other exemplary embodiments include from the one particular value and/or to the other particular value.

[0143] By “comprising” or “containing” or “including” is meant that at least the name compound, element, particle, or method step is present in the composition or article or method, but does not exclude the presence of other compounds, materials, particles, method steps, even if the other such compounds, material, particles, method steps have the same function as what is named.

[0144] In describing example embodiments, terminology will be resorted to for the sake of clarity. It is intended that each term contemplates its broadest meaning as understood by those skilled in the art and includes all technical equivalents that operate in a similar manner to accomplish a similar purpose. It is also to be understood that the mention of one or more steps of a method does not preclude the presence of additional method steps or intervening method steps between those steps expressly identified. Steps of a method may be performed in a different order than those described herein without departing from the scope of the present disclosure. Similarly, it is also to be understood that the mention of one or more components in a device or system does not preclude the presence of additional components or intervening components between those components expressly identified.

[0145] The term “about,” as used herein, means approximately, in the region of, roughly, or around. When the term “about” is used in conjunction with a numerical range, it modifies that range by extending the boundaries above and below the numerical values set forth. In general, the term “about” is used herein to modify a numerical value above and below the stated value by a variance of 10%. In one aspect, the term “about” means plus or minus 10% of the numerical value of the number with which it is being used. Therefore, about 50% means in the range of 45%-55%. Numerical ranges recited herein by endpoints include all numbers and fractions subsumed within that range (e.g., 1 to 5 includes 1, 1.5, 2, 2.75, 3, 3.90, 4, 4.24, and 5). [0146] Similarly, numerical ranges recited herein by endpoints include subranges subsumed within that range (e.g., 1 to 5 includes 1-1.5, 1.5-2, 2-2.75, 2.75-3, 3-3.90, 3.90-4, 4- 4.24, 4.24-5, 2-5, 3-5, 1-4, and 2-4). It is also to be understood that all numbers and fractions thereof are presumed to be modified by the term “about.”

[0147] The following patents, applications, and publications as listed below and throughout this document are hereby incorporated by reference in their entirety herein.

[1] B. Sadhu et al., “A 28-GHz 32-Element TRX Phased-Array IC with Concurrent Dual- Polarized Operation and Orthogonal Phase and Gain Control for 5G Communications,” IEEE JSSC, vol. 52, no. 12, pp. 3373-3391, Dec. 2017.

[2] M. Lokhandwala et al., “A High-Power 24-40-GHz Transmit-Receive Front End for Phased Arrays in 45-nm CMOS SOI,” IEEE TMTT, vol. 68, no. 11, pp. 4775-4786, Nov. 2020.

[3] J. Pang et al., “A 28-GHz CMOS Phased-Array Beamformer Utilizing Neutralized Bi-Directional Technique Supporting Dual-Polarized MIMO for 5GNR,” IEEE JSSC, vol. 55, no. 9, pp. 2371-2386, Sept. 2020.

[4] J. Wang et al., “A 24.25-27.5 GHz Front-End Module with Transformer-Based T/R Switch for 5-G communications,” IEEE Int. Symp. Radio-Freq. Integration Technology, pp. 205-207, Sept. 2020.

[5] F. Wang and H. Wang, “A Broadband Linear Ultra-Compact mm-Wave Power Amplifier With Distributed-Balun Output Network: Analysis and Design,” IEEE JSSC, vol. 56, no. 8, pp. 2308-2323, Aug. 2021.

[6] V. Chauhan and B. Floyd, “A 24-44 GHz UWB LNA for 5G Cellular Frequency Bands,” Global Symp. Millimeter Waves, pp. 1-3, May 2018.